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ICS873039AMLF PDF预览

ICS873039AMLF

更新时间： 2024-11-16 15:34:39
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
15页 215K
描述
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.25 MM HEIGHT, MS-013, MO-119, SOIC-20

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ICS873039AMLF 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：7.50 X 12.80 MM, 2.25 MM HEIGHT, MS-013, MO-119, SOIC-20针数：20
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.18其他特性：ECL MODE: VEE=-2.375V TO -3.8V AT VCC=0V
输入调节：DIFFERENTIALJESD-30 代码：R-PDSO-G20
JESD-609代码：e3长度：12.8 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER功能数量：1
反相输出次数：端子数量：20
实输出次数：4最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：2.65 mm
最大供电电压 (Vsup)：3.8 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：7.5 mmBase Number Matches：1

ICS873039AMLF 数据手册

 浏览型号ICS873039AMLF的Datasheet PDF文件第2页浏览型号ICS873039AMLF的Datasheet PDF文件第3页浏览型号ICS873039AMLF的Datasheet PDF文件第4页浏览型号ICS873039AMLF的Datasheet PDF文件第5页浏览型号ICS873039AMLF的Datasheet PDF文件第6页浏览型号ICS873039AMLF的Datasheet PDF文件第7页 
PRELIMINARY  
ICS873039  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, ÷2/4,÷4/6,  
LVPECL-TO-3.3V LVPECL / ECL CLOCK GENERATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS873039 is a low skew, high performance • 2 divide by 2/4 differential 3.3V LVPECL outputs;  
ICS  
LVPECL-to-3.3V LVPECL / ECL Clock Genera-  
tor/Divider and a member of the HiPerClockS™  
family of High Performance Clock Solutions from  
ICS. The ICS873039 has one LVPECL differen-  
2 divide by 4/6 differential 3.3V LVPECL outputs  
HiPerClockS™  
• 1 differential PCLK, nPCLK input pair  
• PCLK, nPCLK pair can accept the following differential  
input levels: LVPECL, LVDS, CML, SSTL  
tial clock input pair. The PCLK, nPCLK pair can accept  
LVPECL, LVDS, CML, SSTL input levels.The clock enable is  
internally synchronized to eliminate runt pulses on the  
outputs during asynchronous assertion/deassertion of the  
clock enable pin.  
• Maximum input frequency: 3.2GHz  
• Translates any single ended input signal (LVCMOS, LVTTL,  
GTL) to LVPECL levels with resistor bias on nPCLK input  
Guaranteed output and part-to-part skew characteristics  
make the ICS873039 ideal for clock distribution applications  
demanding well defined performance and repeatability.  
• Output skew: 20ps (typical)  
• Part-to-part skew: 85ps (typical)  
• Propagation delay: 690ps (typical)  
• LVPECL mode operating voltage supply range:  
VCC = 2.375V to 3.8V, VEE = 0V  
• ECL mode operating voltage supply range:  
VCC = 0V, VEE = -3.8V to -2.375V  
• -40°C to 85°C ambient operating temperature  
• Compatible with MC100LVEL39  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
DIV_SELA  
VCC  
nEN  
DIV_SELB  
PCLK  
nPCLK  
VBB  
VCC  
1
2
3
4
5
6
7
8
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
QA0  
nQA0  
QA1  
nQA1  
QB2  
nQB2  
QB3  
nQB3  
VEE  
QA0  
nQA0  
÷2, ÷4  
PCLK  
nPCLK  
R
QA1  
nQA1  
MR  
VCC  
nc  
9
10  
DIV_SELA  
nEN  
QB2  
nQB2  
ICS873039  
20-Lead SOIC, 300MIL  
M Package  
÷4, ÷6  
R
QB3  
nQB3  
MR  
DIV_SELB  
VBB  
7.5mm x 12.8mm x 2.25 package body  
TopView  
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
873039AM  
www.icst.com/products/hiperclocks.html  
REV. A MAY 3, 2004  
1
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