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ICS87339AG-01LF PDF预览

ICS87339AG-01LF

更新时间: 2024-11-16 21:13:43
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
15页 150K
描述
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 X 0.92 MM, TSSOP-20

ICS87339AG-01LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.53输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:6.5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:20实输出次数:4
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):3 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.05 ns
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

ICS87339AG-01LF 数据手册

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ICS87339-01  
Integrated  
Circuit  
Systems, Incꢀ  
LOW SKEW, ÷2/4,÷4/6,  
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS87339-01 is a low skew, high perfor- 2 divide by 2/4 differential 3.3V LVPECL outputs;  
mance Differential-to-3.3V LVPECL / ECL Clock  
Generator/Divider and a member of the  
HiPerClockS™ family of High Performance Clock  
Solutions from ICS. The ICS87339-01 has one  
2 divide by 4/6 differential 3.3V LVPECLoutputs  
HiPerClockS™  
1 differential CLK, nCLK input pair  
CLK, nCLK pair can accept the following differential  
differential clock input pair. The CLK, nCLK pair can accept  
most standard differential input levels. The clock enable is  
internally synchronized to eliminate runt pulses on the  
outputs during asynchronous assertion/deassertion of the  
clock enable pin.  
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL  
Maximum input frequency: 1GHz  
Translates any single ended input signal (LVCMOS, LVTTL,  
GTL) to LVPECL levels with resistor bias on nCLK input  
Guaranteed output and part-to-part skew characteristics  
make the ICS87339-01 ideal for clock distribution applications  
demanding well defined performance and repeatability.  
Output skew: 50ps (maximum)  
Part-to-part skew: 200ps (maximum)  
LVPECLmode operating voltage supply range:  
VCC = 3V to 3.8V, VEE = 0V  
ECL mode operating voltage supply range:  
VCC = 0V, VEE = -3V to -3.8V  
0°C to 70°C ambient operating temperature  
Industrial temperature information available upon request  
Compatible with MC100LVEL39  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
DIV_SELA  
VCC  
nCLK_EN  
DIV_SELB  
CLK  
VCC  
1
2
3
4
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
QA0  
nQA0  
QA0  
nQA0  
QA1  
nQA1  
QB0  
nQB0  
QB1  
nQB1  
VEE  
D
nCLK_EN  
÷2, ÷4  
QA1  
nQA1  
Q
R
nCLK  
nc  
MR  
VCC  
nc  
5
6
7
8
9
10  
LE  
CLK  
nCLK  
DIV_SELA  
QB0  
nQB0  
ICS87339-01  
20-Lead TSSOP, G Package  
6.5mm x 4.4mm x 0.92mm  
body package  
÷4, ÷6  
QB1  
nQB1  
R
MR  
Top View  
DIV_SELB  
ICS87339-01  
20-Lead SOIC, M Package  
7.5mm x 12.8mm x 2.25  
package body  
Top View  
87339AG-01  
www.icst.com/products/hiperclocks.html  
REV. A AUGUST 15, 2002  
1

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