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ICS87339AMI-11LFT PDF预览

ICS87339AMI-11LFT

更新时间: 2024-09-29 21:06:27
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
14页 648K
描述
Low Skew Clock Driver, 87339 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.25 MM HEIGHT, ROHS COMPLIANT, MO-119, MS-013, SOIC-20

ICS87339AMI-11LFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.1
系列:87339输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.8 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:20
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:2.1 ns传播延迟(tpd):2.1 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.038 ns
座面最大高度:2.65 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmBase Number Matches:1

ICS87339AMI-11LFT 数据手册

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ICS87339I-11  
LOW SKEW,  
÷2/4,÷4/5/6,  
DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS87339I-11 is a low skew, high perfor- Dual ÷2, ÷4 differential 3.3V LVPECL outputs;  
ICS  
mance Differential-to-3.3V LVPECL Clock Gen-  
erator/Divider and a member of the HiPerClockS™  
family of High Performance Clock Solutions  
from IDT. The ICS87339I-11 has one differen-  
Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs  
HiPerClockS™  
One differential CLK, nCLK input pair  
CLK, nCLK pair can accept the following differential  
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL  
tial clock input pair. The CLK, nCLK pair can accept most  
standard differential input levels. The clock enable is  
internally synchronized to eliminate runt pulses on the  
outputs during asynchronous assertion/deassertion of the  
clock enable pin.  
Maximum clock input frequency: 1GHz  
Translates any single ended input signal (LVCMOS, LVTTL,  
GTL) to LVPECL levels with resistor bias on nCLK input  
Guaranteed output and part-to-part skew characteristics  
make the ICS87339I-11 ideal for clock distribution applica-  
tions demanding well defined performance and repeatability.  
Output skew: 35ps (maximum)  
Part-to-part skew: 385ps (maximum)  
Bank skew: Bank A - 20ps (maximum)  
Bank B - 20ps (maximum)  
Propagation delay: 2.1ns (maximum)  
LVPECL mode operating voltage supply range:  
VCC = 3V to 3.6V, VEE = 0V  
Available in both standard (RoHS5) and lead-free (RoHS 6)  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
DIV_SELA  
VCC  
nCLK_EN  
DIV_SELB0  
CLK  
nCLK  
RESERVED  
MR  
VCC  
DIV_SELB1  
DIV_SELA  
VCC  
1
2
3
4
5
6
7
8
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
QA0  
nQA0  
QA0  
nQA0  
QA1  
nQA1  
QB0  
nQB0  
QB1  
nQB1  
VEE  
D
nCLK_EN  
÷2, ÷4  
R
QA1  
nQA1  
Q
LE  
CLK  
nCLK  
9
10  
QB0  
nQB0  
ICS87339I-11  
÷4, ÷5, ÷6  
20-LeadTSSOP  
6.50mm x 4.40mm x 0.92 package body  
G Package  
QB1  
nQB1  
R
MR  
DIV_SELB0  
DIV_SELB1  
Top View  
20-Lead SOIC, 300MIL  
7.5mm x 12.8mm x 2.25mm package body  
M Package  
Top View  
87339AGI-11  
1
REV.A March 3, 2009  

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