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ICS8733Y-01 PDF预览

ICS8733Y-01

更新时间: 2024-09-29 19:09:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
9页 102K
描述
PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32

ICS8733Y-01 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LQFP, QFP32,.35SQ,32
针数:32Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.47
输入调节:MUXJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.036 A
功能数量:1反相输出次数:
端子数量:32实输出次数:2
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP32,.35SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.01 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
最小 fmax:700 MHzBase Number Matches:1

ICS8733Y-01 数据手册

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ADVANCED INFORMATION  
ICS8733-01  
FORWARD ERROR CORRECTION  
CLOCK GENERATOR  
Integrated  
Circuit  
Systems, Incꢀ  
GENERAL DESCRIPTION  
FEATURES  
The ICS8733-01 is a dual output clock genera-  
Clock synthesis of 14/15 or 15/14 of the input reference  
clock to be utilized in Forward Error Correction (FEC)  
applications  
tor and a member of the HiPerClockSfamily of  
High Performance Clock Solutions from ICS.  
The ICS8733-01 is designed to be used for ap-  
plications utilizing Forward Error Correction  
HiPerClockS™  
Fully integrated PLL  
(FEC) designs. The ICS8733-01 generates a 14/15 or a 15/  
14 output clock based upon the input reference clock in order  
to incorporate the FEC capability required by the application.  
Accepts any differential input signal (PECL, HSTL, LVDS,  
SSTL, etc.)  
Dual differential 3.3V LVPECLoutputs  
38.88MHz to 700MHz output frequency  
Clock generator is performed by a fully integrated and  
low-jitter phase-locked loop. The ICS8733-01 accepts any  
differential signal as its input with an input reference fre-  
quency range of 36.27MHz to 750MHz. There are two  
LVPECL outputs which can generate output frequencies of  
38.88MHz to 700MHz.  
PLL bypass and test modes that support in-circuit testing  
and on-chip functional block characterization  
LVTTL / LVCMOS control inputs  
3.3V supply voltage  
32 lead low profile QFB (LQFP), 7mm x 7mm x 1.4mm  
package body, 0.8mm package lead pitch  
0°C to 70°C ambient operating temperature  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
DIV_SEL0  
DIV_SEL1  
MR  
32 31 30 29 28 27 26 25  
PLL_SEL  
nc  
FEC_NSEL  
FEC_MSEL  
VEE  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
REF_CLK  
nREF_CLK  
VDDA  
N ”  
÷14  
REF_CLK  
0
1
nREF_CLK  
VDDA  
ICS8733-01  
÷15  
VEE  
DIV_SEL0  
DIV_SEL1  
nc  
TEST_SEL  
TEST_EN  
GND  
FEC_NSEL  
MR  
9
10 11 12 13 14 15 16  
0 0  
0 1  
1 0  
1 1  
÷¼  
÷1  
÷2  
÷4  
0
1
FOUT1  
nFOUT1  
PLL  
FOUT0  
nFOUT0  
32-Lead LQFP  
Y Package  
Top View  
÷15  
0
1
0
1
÷14  
TEST  
M ”  
FEC_MSEL  
TEST_SEL  
TEST_EN  
The Advance Information presented herein represents a product currently in design or being considered for design. The noted characteristics are  
design targets. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
8733-01  
www.icst.com/products/hipercocks.html  
JULY 17, 2001  
1

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