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ICS8735AM-21LF PDF预览

ICS8735AM-21LF

更新时间： 2024-09-29 14:51:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
20页 739K
描述
PLL Based Clock Driver, 8735 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-20

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ICS8735AM-21LF 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：7.50 X 12.80 MM, 2.30 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-20针数：20
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.71
Is Samacsys：N系列：8735
输入调节：DIFFERENTIAL MUXJESD-30 代码：R-PDSO-G20
JESD-609代码：e3长度：12.8 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER湿度敏感等级：1
功能数量：1反相输出次数：
端子数量：20实输出次数：1
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：4.2 ns
传播延迟（tpd）：4.2 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.02 ns座面最大高度：2.65 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：7.5 mm
最小 fmax：700 MHzBase Number Matches：1

ICS8735AM-21LF 数据手册

 浏览型号ICS8735AM-21LF的Datasheet PDF文件第2页浏览型号ICS8735AM-21LF的Datasheet PDF文件第3页浏览型号ICS8735AM-21LF的Datasheet PDF文件第4页浏览型号ICS8735AM-21LF的Datasheet PDF文件第5页浏览型号ICS8735AM-21LF的Datasheet PDF文件第6页浏览型号ICS8735AM-21LF的Datasheet PDF文件第7页 
700MHz, DIFFERENTIAL-TO-3.3V LVPECL  
ZERO DELAY CLOCK GENERATOR  
ICS8735-21  
General Description  
Features  
The ICS8735-21 is a highly versatile 1:1 Differential-  
• One differential 3.3V LVPECL output pair  
One differential feedback output pair  
S
IC  
to-3.3V LVPECL clock generator and a member of  
the HiPerClockS™family of High Performance Clock  
Solutions from IDT. The CLK, nCLK pair can accept  
most standard differential input levels. The  
HiPerClockS™  
• Differential CLK/nCLK input pair  
• CLK/nCLK pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL  
ICS8735-21 has a fully integrated PLL and can be configured as  
zero delay buffer, multiplier or divider, and has an output frequency  
range of 31.25MHz to 700MHz. The reference divider, feedback  
divider and output divider are each programmable, thereby  
allowing for the following output-to-input frequency ratios: 8:1, 4:1,  
2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to  
achieve “zero delay” between the input clock and the output  
clocks. The PLL_SEL pin can be used to bypass the PLL for  
system test and debug purposes. In bypass mode, the reference  
clock is routed around the PLL and into the internal output  
dividers.  
• Output frequency range: 31.25MHz to 700MHz  
• Input frequency range: 31.25MHz to 700MHz  
• VCO range: 250MHz to 700MHz  
• External feedback for “zero delay” clock regeneration  
with configurable frequencies  
• Programmable dividers allow for the following output-to-input  
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8  
• Cycle-to-cycle jitter: 25ps (maximum)  
• Static phase offset: 50ps 100ps  
• Full 3.3V supply voltage  
• 0°C to 70°C ambient operating temperature  
• Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Pin Assignments  
CLK  
nCLK  
MR  
1
2
20 nc  
19  
SEL1  
3
4
18 SEL0  
VCC  
17  
VCC  
nFB_IN  
FB_IN  
SEL2  
5
6
7
16 PLL_SEL  
15  
14  
13  
12  
11  
VCCA  
SEL3  
VEE  
nQFB  
QFB  
8
V
CCO  
9
10  
Q
nQ  
Block Diagram  
ICS8735-21  
Pullup  
PLL_SEL  
Q
nQ  
20-Lead SOIC  
7.5mm x 12.8mm x 2.3mm package body  
M Package  
÷1, ÷2, ÷4, ÷8,  
0
÷16, ÷32,÷64  
Pulldown  
Pullup  
CLK  
nCLK  
QFB  
nQFB  
1
Top View  
PLL  
8:1, 4:1, 2:1, 1:1,  
1:2, 1:4, 1:8  
32 31 30 29 28 27 26 25  
Pulldown  
Pullup  
FB_IN  
nFB_IN  
1
2
SEL0  
VCCO  
24  
23  
ICS8735-21  
SEL1  
nc  
nc  
32-Lead VFQFN  
Q
35mm x 5mm x 0.925mm22  
nQ  
QFB  
4
nc  
21  
package body  
K Package  
Top View  
Pulldown  
Pulldown  
Pulldown  
Pulldown  
Pulldown  
SEL0  
SEL1  
SEL2  
SEL3  
MR  
CLK  
5
6
7
8
20  
19  
18  
17  
nCLK  
nc  
nQFB  
nc  
MR  
VCCO  
9
10 11 12 13 14 15 16  
IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR  
1
ICS8735AM-21 REV. A JULY 31, 2008  
1234567...20

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 		700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
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