Datasheet > ICS8735AY-01

ICS8735AY-01

更新时间： 2024-09-28 21:55:19

品牌	Logo	应用领域
矽成 - ICSI		时钟发生器逻辑集成电路驱动
页数	文件大小	规格书
17页	287K
描述
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

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ICS8735AY-01 数据手册

ICS8735-01

Integrated

Circuit

Systems, Inc.

1:5 DIFFERENTIAL

TO-3.3V LVPECL

ZERO

ELAY

CLOCK

GENERATOR

GENERAL DESCRIPTION

FEATURES

The ICS8735-01 is a highly versatile 1:5 Differ- • 5 differential 3.3V LVPECL outputs

ICS

ential-to-3.3V LVPECL clock generator and a

• Selectable differential clock inputs

HiPerClockS™

member of the HiPerClockS™ family of High

Performance Clock Solutions from ICS. The

ICS8735-01 has a fully integrated PLL and can

• CLKx, nCLKx pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

be configured as zero delay buffer, multiplier or divider, and

has an output frequency range of 31.25MHz to 700MHz.The

reference divider, feedback divider and output divider are each

programmable, thereby allowing for the following output-to-

input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The

external feedback allows the device to achieve “zero delay”

between the input clock and the output clocks.The PLL_SEL

pin can be used to bypass the PLL for system test and debug

purposes. In bypass mode, the reference clock is routed

around the PLL and into the internal output dividers.

• Output frequency range: 31.25MHz to 700MHz

• Input frequency range: 31.25MHz to 700MHz

• VCO range: 250MHz to 700MHz

• Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• External feedback for “zero delay” clock regeneration

with configurable frequencies

• Cycle-to-cycle jitter: 25ps (maximum)

• Output skew: 25ps (maximum)

• Static phase offset: 50ps 100ps

• 3.3V supply voltage

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

BLOCK DIAGRAM

PIN ASSIGNMENT

nQ0

PLL_SEL

nQ1

÷1, ÷2, ÷4, ÷8,

÷16, ÷32, ÷64

CLK0

nCLK0

32 31 30 29 28 27 26 25

nQ2

SEL0

SEL1

V^CCO

CLK1

nQ3

nCLK1

CLK0

nQ3

PLL

nQ4

nCLK0

CLK1

CLK_SEL

ICS8735-01

nQ2

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

nCLK1

CLK_SEL

FB_IN

nFB_IN

nQ1

V^CCO

10 11 12 13 14 15 16

SEL0

SEL1

SEL2

SEL3

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

TopView

32-LeadVFQFN

5mm x 5mm x 0.95 package body

K Package

TopView

8735AY-01

www.icst.com/products/hiperclocks.html

REV. F NOVEMBER 12, 2004

12 3 4 5 6 7...17

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与ICS8735AY-01相关器件

型号	品牌	获取价格	描述	数据表
ICS8735AY-01LFT	IDT	获取价格	PLL Based Clock Driver, 8735 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7
ICS8735AY-01T	ICSI	获取价格	1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
ICS8735AY-31LF	IDT	获取价格	PLL Based Clock Driver, 8735 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7
ICS8735AYI-01	IDT	获取价格	PLL Based Clock Driver, 8735 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7
ICS8735AYI-31LFT	IDT	获取价格	PLL Based Clock Driver, 8735 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7
ICS87366AMLF	IDT	获取价格	PLL Based Clock Driver, 87366 Series, 6 True Output(s), 0 Inverted Output(s), PDSO24, 7.50
ICS87366AMLFT	IDT	获取价格	PLL Based Clock Driver, 87366 Series, 6 True Output(s), 0 Inverted Output(s), PDSO24, 7.50
ICS8737-11	ICSI	获取价格	LOW SKEW ±1/±2 DIFFERENTIAL-TO- 3.3V LVPECL C
ICS8737-11-LF	IDT	获取价格	Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.9
ICS8737-11T	IDT	获取价格	Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.9

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