Datasheet > ICS8737-11

ICS8737-11

更新时间： 2024-09-28 22:13:39

品牌	Logo	应用领域
矽成 - ICSI		时钟发生器
页数	文件大小	规格书
13页	129K
描述
LOW SKEW ±1/±2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR

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中文翻译

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数据手册

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ICS8737-11 数据手册

ICS8737-11

Integrated

Circuit

Systems, Incꢀ

LOW SKEW

÷1/÷2

DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR

GENERAL DESCRIPTION

FEATURES

The ICS8737-11 is a low skew, high performance • 2 divide by 1 differential 3.3V LVPECL outputs;

Differential-to-3.3V LVPECL Clock Generator/

Divider and a member of the HiPerClockS™

family of High Performance Clock Solutions from

ICS. The ICS8737-11 has two selectable clock

2 divide by 2 differential 3.3V LVPECLoutputs

HiPerClockS™

• Selectable CLK, nCLK or LVPECL clock inputs

• CLK, nCLK pair can accept the following differential input

inputs. The CLK, nCLK pair can accept most standard differ-

ential input levels. The PCLK, nPCLK pair can accept

LVPECL, CML, or SSTL input levels.The clock enable is

internally synchronized to eliminate runt pulses on the

outputs during asynchronous assertion/deassertion of the

clock enable pin.

levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

• PCLK, nPCLK supports the following input types:

LVPECL, CML, SSTL

• Maximum output frequency up to 650MHz

• Translates any single ended input signal (LVCMOS, LVTTL,

GTL) to LVPECL levels with resistor bias on nCLK input

Guaranteed output and part-to-part skew characteristics

make the ICS8737-11 ideal for clock distribution applications

demanding well defined performance and repeatability.

• Output skew: 60ps (maximum)

• Part-to-part skew: 200ps (maximum)

• Bank skew: Bank A - 20ps (maximum),

Bank B - 35ps (maximum)

• Propagation delay: 1.7ns (maximum)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

BLOCK DIAGRAM

PIN ASSIGNMENT

QA0

nQA0

VEE

CLK_EN

CLK_SEL

CLK

QA0

nQA0

V^CC

QA1

nQA1

QB0

nQB0

V^CC

CLK_EN

QA1

nQA1

nCLK

PCLK

nPCLK

CLK

nCLK

PCLK

nPCLK

÷1

÷2

V^CC

QB1

nQB1

QB0

nQB0

CLK_SEL

ICS8737-11

20-Lead TSSOP

6.50mm x 4.40mm x 0.92 package body

G Package

QB1

nQB1

Top View

8737AG-11

www.icst.com/products/hiperclocks.html

REV. A JULY 13, 2001

12 3 4 5 6 7...13

中文翻译

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与ICS8737-11相关器件

型号	品牌	获取价格	描述	数据表
ICS8737-11-LF	IDT	获取价格	Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.9
ICS8737-11T	IDT	获取价格	Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.9
ICS8737-11T-LF	IDT	获取价格	Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.9
ICS8737AG-11	ICSI	获取价格	LOW SKEW ±1/±2 DIFFERENTIAL-TO- 3.3V LVPECL C
ICS8737AG-11LF	IDT	获取价格	Low Skew Clock Driver, 8737 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X
ICS8737AG-11T	ICSI	获取价格	LOW SKEW ±1/±2 DIFFERENTIAL-TO- 3.3V LVPECL C
ICS8737AGI-11	IDT	获取价格	Low Skew Clock Driver, 8737 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X
ICS8737AGI-11LF	IDT	获取价格	Low Skew Clock Driver, 8737 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X
ICS8737AGI-11LFT	IDT	获取价格	Low Skew Clock Driver, 8737 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X
ICS8737AGT-11	IDT	获取价格	Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, MO-153, TSSOP

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