ICS873990
LOW VOLTAGE, LVCMOS/
CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
FEATURES
GENERAL DESCRIPTION
• 14 differential LVPECL outputs
The ICS873990 is a low voltage, low skew, 3.3V
ICS
LVPECL/ECL Clock Generator and a member
of the HiPerClockS™family of High Performance
• Selectable crystal oscillator interface or TEST_CLK inputs
HiPerClockS™
Clock Solutions from ICS. The ICS873990 has • TEST_CLK accepts the following input levels:
two selectable clock inputs. The XTAL1 and
LVCMOS, LVTTL
XTAL2 are used to interface to a crystal and the TEST_CLK
pin can accept a LVCMOS or LVTTL input. This device has a
fully integrated PLL along with frequency configurable out-
puts. An external feedback input and output regenerates
clocks with “zero delay”.
• Output frequency: 400MHz (maximum)
• Crystal input frequency range: 10MHz to 25MHz
• VCO range: 200MHz to 800MHz
• Output skew: 250ps (maximum)
• Cycle-to-cyle jitter: 50ps (typical)
The four independent banks of outputs each have their own
output dividers, which allow the device to generate a multi-
tude of different bank frequency ratios and output-to-input
frequency ratios. The output frequency range is 25MHz to
400MHz and the input frequency range is 6.25MHz to
125MHz.The PLL_SEL input can be used to bypass the PLL
for test and system debug purposes. In bypass mode, the
input clock is routed around the PLL and into the internal out-
put dividers.
• LVPECL mode operating voltage supply range:
VCC = 3.135V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -3.135V
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
• Lead-Free package fully RoHS compliant
The ICS873990 also has a SYNC output which can be used
for system synchronization purposes. It monitors Bank A and
Bank C outputs for coincident rising edges and signals a pulse
per the timing diagrams in this data sheet.This feature is used
primarily in applications where Bank A and Bank C are run-
ning at different frequencies, and is particularly useful when
they are running at non-integer multiples of each other.
PIN ASSIGNMENT
Example Applications:
1. Line Card Multiplier: Multiply 19.44MHz from a back-plane
to 77.76MHz on the line card ASIC and Serdes.
39 38 37 36 35 34 33 32 31 30 29 28 27
nQB3
QB3
40
41
42
43
44
45
46
47
48
49
50
51
52
26
25
24
23
22
21
20
19
18
17
16
15
14
QC1
2. Zero Delay Buffer: Fan out up to thirteen 100MHz copies
from a reference clock to multiple processing units on an
embedded system.
nQC1
QC0
VCCO
nQA0
nQC0
VCCO
QD1
QA0
nQA1
QA1
ICS873990
nQD1
QD0
nQA2
QA2
nQD0
VCCO
QFB
nQFB
VCCA
nQA3
QA3
SYNC_SEL
VCO_SEL
1
2
3
4
5
6
7 8 9 10 11 12 13
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
TopView
873990AY
www.icst.com/products/hiperclocks.html
REV. B JUNE 13, 2005
1