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ICS8731CY-01LF PDF预览

ICS8731CY-01LF

更新时间: 2024-11-16 21:06:03
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
17页 281K
描述
PLL Based Clock Driver, 11 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48

ICS8731CY-01LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48针数:48
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.3输入调节:DIFFERENTIAL
JESD-30 代码:S-PQFP-G48JESD-609代码:e3
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:48实输出次数:11
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):4.25 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.2 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
Base Number Matches:1

ICS8731CY-01LF 数据手册

 浏览型号ICS8731CY-01LF的Datasheet PDF文件第2页浏览型号ICS8731CY-01LF的Datasheet PDF文件第3页浏览型号ICS8731CY-01LF的Datasheet PDF文件第4页浏览型号ICS8731CY-01LF的Datasheet PDF文件第5页浏览型号ICS8731CY-01LF的Datasheet PDF文件第6页浏览型号ICS8731CY-01LF的Datasheet PDF文件第7页 
ICS8731-01  
LOW SKEW, 1-TO-11 DIFFERENTIAL-TO-3.3V LVPECL  
CLOCK MULTIPLIER / ZERO DELAY BUFFER  
FEATURES  
GENERAL DESCRIPTION  
The ICS8731-01 is  
a
low voltage, low skew, Eleven differential 3.3V LVPECL outputs  
1-to-11 Differential-to-3.3V LVPECL Clock Multiplier/Zero  
Delay Buffer. With output frequencies up to 700MHz the  
ICS8731-01 is targeted at high performance clock  
applications. Along with a fully integrated PLL the ICS8731-  
01 contains frequency configurable, differential outputs  
and external feedback inputs for multiplying clock  
frequencies and regenerating clocks with “zero delay”.  
Frequency multiplication is achieved by utilizing the  
separate feedback and clock output dividers. The value of  
the multiplier is determined by the ratio of the feedback  
divider, M, to the output divider,N. For multiplier values  
greater than 1, M must be greater than N. For multiplier  
values less than 1,M must be less than N. The zero delay  
mode is achieved with M and N at equal values. The divide  
values of the clock and feedback outputs are controlled by  
the DIV_SEL0:2 and FB_SEL0:1 inputs, respectively. The  
ICS8731-01 accepts any differential signal and translates  
it to differential 3.3V LVPECL output levels.  
Differential reference clock input pair  
REF_CLK, nREF_CLK pair can accept the following  
differential input levels: LVPECL, LVDS, LVHSTL, SSTL,  
HCSL  
Maximum output frequency: 700MHz  
Maximum reference clock input frequency: 200MHz  
VCO range: 250MHz - 700MHz  
Accepts any single-ended input signal with a resistor bias  
on nCLK input  
External feedback for zero delay capabilitiy  
Output skew: 70ps (maximum)  
Cycle-to-cycle jitter: 65ps (maximum)  
Full 3.3V operating supply  
0°C to 70°C ambient operating temperature  
Available in both standard and lead-free RoHS compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
DIV_SEL0  
DIV_SEL1  
48 47 46 45 44 43 42 41 40 39 38 37  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VCCO  
nQ3  
Q3  
MR  
2
VCCO  
DIV_SEL2  
3
Q8  
nQ8  
4
nQ2  
Q2  
÷1  
÷2  
÷4  
÷6  
÷8  
100  
000  
001  
010  
011  
5
Q9  
Q0:Q9  
6
VEE  
nQ9  
nQ0:nQ9  
ICS8731-01  
7
nQ1  
Q1  
VEE  
0
1
8
Q10/FB_OUT  
nQ10/nFB_OUT  
VCCO  
REF_CLK  
nREF_CLK  
9
nQ0  
Q0  
PLL  
10  
11  
12  
FB_IN  
nFB_IN  
÷2  
÷4  
÷6  
÷8  
00  
01  
10  
11  
VCCO  
nc  
FB_IN  
Q10/FB_OUT  
nQ10/nFB_OUT  
nFB_IN  
13 14 15 16 17 18 19 20 21 22 23 24  
PLL_SEL  
MR  
FB_SEL1  
FB_SEL0  
48-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
Top View  
8731CY-01  
www.idt.com  
REV. B JULY 27, 2010  
1

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