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ICS8725AYI-01 PDF预览

ICS8725AYI-01

更新时间: 2024-09-29 14:51:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
16页 515K
描述
PLL Based Clock Driver, 8725 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32

ICS8725AYI-01 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Transferred零件包装代码:QFP
包装说明:LQFP,针数:32
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.36Is Samacsys:N
系列:8725输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:32实输出次数:5
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):4.5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.05 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
最小 fmax:31.25 MHzBase Number Matches:1

ICS8725AYI-01 数据手册

 浏览型号ICS8725AYI-01的Datasheet PDF文件第2页浏览型号ICS8725AYI-01的Datasheet PDF文件第3页浏览型号ICS8725AYI-01的Datasheet PDF文件第4页浏览型号ICS8725AYI-01的Datasheet PDF文件第5页浏览型号ICS8725AYI-01的Datasheet PDF文件第6页浏览型号ICS8725AYI-01的Datasheet PDF文件第7页 
ICS8725I-01  
1:5 DIFFERENTIAL-TO-HSTL  
ZERO DELAY CLOCK GENERATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS8725I-01 is a highly versatile 1:5 Differ-  
5 differential HSTL outputs  
ICS  
ential-to-HSTL Clock Generator and a member  
of the HiPerClockS™family of High Performance  
Clock Solutions from ICS.The ICS8725I-01 has  
a fully integrated PLL and can be configured as  
Selectable differential CLKx, nCLKx input pairs  
HiPerClockS™  
CLKx, nCLKx pairs can accept the following differential  
input levels: LVDS, LVPECL, HSTL, SSTL, HCSL  
zero delay buffer, multiplier or divider, and has an output fre-  
quency range of 31.25MHz to 630MHz.The reference divider,  
feedback divider and output divider are each programmable,  
thereby allowing for the following output-to-input frequency  
ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback  
allows the device to achieve “zero delay” between the input  
clock and the output clocks. The PLL_SEL pin can be used  
to bypass the PLL for system test and debug purposes. In  
bypass mode, the reference clock is routed around the PLL  
and into the internal output dividers.  
Output frequency range: 31.25MHz to 630MHz  
Input frequency range: 31.25MHz to 630MHz  
VCO range: 250MHz to 630MHz  
External feedback for “zero delay” clock regeneration  
with configurable frequencies  
Programmable dividers allow for the following output-to-input  
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8  
Static phase offset: 30ps ± 125ps  
Cycle-to-cycle jitter: 35ps (maximum)  
Output skew: 50ps (maximum)  
3.3V core, 1.8V output operating supply  
-40°C to 85°C ambient operating temperature  
Available in both standard (RoHS5) and lead-free (RoHS 6)  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
PLL_SEL  
Q0  
nQ0  
Q1  
nQ1  
÷1, ÷2, ÷4, ÷8,  
32 31 30 29 28 27 26 25  
0
1
CLK0  
nCLK0  
÷16, ÷32,÷64  
Q2  
nQ2  
0
1
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
SEL0  
SEL1  
VDDO  
Q3  
CLK1  
nCLK1  
Q3  
nQ3  
CLK0  
nQ3  
Q2  
PLL  
nCLK0  
CLK1  
Q4  
nQ4  
ICS8725I-01  
CLK_SEL  
nQ2  
Q1  
8:1, 4:1, 2:1, 1:1,  
1:2, 1:4, 1:8  
nCLK1  
CLK_SEL  
FB_IN  
nFB_IN  
nQ1  
VDDO  
MR  
9
10 11 12 13 14 15 16  
SEL0  
SEL1  
SEL2  
SEL3  
MR  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
TopView  
8725AYI-01  
1
REV.A DECEMVER 19, 2007  

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