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ICS8701AYI-01T PDF预览

ICS8701AYI-01T

更新时间: 2024-09-26 18:31:59
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
8页 219K
描述
Low Skew Clock Driver, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48

ICS8701AYI-01T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP,针数:48
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.15输入调节:STANDARD
JESD-30 代码:S-PQFP-G48JESD-609代码:e0
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:48实输出次数:20
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):240传播延迟(tpd):3.5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.3 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:7 mm
Base Number Matches:1

ICS8701AYI-01T 数据手册

 浏览型号ICS8701AYI-01T的Datasheet PDF文件第2页浏览型号ICS8701AYI-01T的Datasheet PDF文件第3页浏览型号ICS8701AYI-01T的Datasheet PDF文件第4页浏览型号ICS8701AYI-01T的Datasheet PDF文件第5页浏览型号ICS8701AYI-01T的Datasheet PDF文件第6页浏览型号ICS8701AYI-01T的Datasheet PDF文件第7页 
ICS8701I-01  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, ÷1, ÷2  
LVCMOS/ LVTTL CLOCK GENERATOR W/POLARITY CONTROL  
GENERAL DESCRIPTION  
FEATURES  
The ICS8701I-01 is a low skew, ÷1, ÷2 LVCMOS/  
• 20 LVCMOS/LVTTL outputs, 7typical output impedance  
• 1 LVCMOS/LVTTL clock input  
ICS  
LVTTL Clock Generator and a member of the  
HiPerClockS™  
HiPerClockS™family of High Performance Clock  
Solutions from ICS.The low impedance LVCMOS  
outputs are designed to drive 50series or paral-  
• Maximum output frequency: 250MHz  
• Selectable inverting and non-inverting outputs  
lel terminated transmission lines. The effective fanout can be  
increased from 20 to 40 by utilizing the ability of the outputs to  
drive two series terminated lines.  
• Bank enable logic allows unused banks to be  
disabled in reduced fanout applications  
The divide select inputs, DIV_SELx, control the output frequency  
of each bank. The outputs can be utilized in the ÷1, ÷2 or a  
combination of ÷1 and ÷2 modes.The master reset/output en-  
able input, nMR/OE, resets the internal dividers and controls  
the active and high impedance states of all outputs.The output  
polarity inputs, INV0:1, control the polarity (inverting or non-in-  
verting) of the outputs of each bank. Outputs QA0:QA4 are in-  
verting for every combination of the INV0:1 input. The timing  
relationship between the inverting and non-inverting outputs at  
different frequencies is shown in theTiming Diagrams.  
• Output skew: 300ps (maximum)  
• Part-to-part skew: 700ps (maximum)  
• Bank skew: 250ps (maximum)  
• Multiple frequency skew: 350ps (maximum)  
• 3.3V or mixed 3.3V input, 2.5V output operating supply  
• -40°C to 85°C ambient operating temperature  
The ICS8701I-01 is characterized at 3.3V and mixed 3.3V input  
supply, and 2.5V output supply operating modes. Guaranteed  
bank, output and part-to-part skew characteristics make the  
ICS8701I-01 ideal for those clock distribution applications de-  
manding well defined performance and repeatability.  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
1
0
÷1  
÷2  
CLK  
QA0:QA4  
QB0:QB4  
QC0:QC4  
QD0:QD4  
48 47 46 45 44 43 42 41 40 39 38 37  
DIV_SELA  
QC3  
VDDOC  
QC4  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
QB1  
VDDOB  
QB0  
QA4  
VDDOA  
QA3  
GND  
QA2  
GND  
QA1  
VDDOA  
QA0  
1
0
2
3
QD0  
4
DIV_SELB  
DIV_SELC  
VDDOD  
QD1  
5
6
1
0
ICS8701I-01  
GND  
QD2  
7
8
GND  
QD3  
9
10  
11  
12  
1
0
VDDOD  
QD4  
13 14 15 16 17 18 19 20 21 22 23 24  
DIV_SELD  
nMR/OE  
Output  
Polarity  
Control  
INV0  
INV1  
48-Pin LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
TopView  
8701AYI-01  
www.icst.com/products/hiperclocks.html  
REV. A MARCH 4, 2004  
1

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