Datasheet > ICS8705BYLFT

ICS8705BYLFT

更新时间： 2024-09-28 22:09:27

品牌	Logo	应用领域
矽成 - ICSI		时钟发生器逻辑集成电路驱动
页数	文件大小	规格书
17页	293K
描述
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

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ICS8705BYLFT 数据手册

ICS8705

Integrated

Circuit

Systems, Inc.

ZERO

ELAY, DIFFERENTIAL

TO-LVCMOS/LVTTL

LOCK

GENERATOR

GENERAL DESCRIPTION

FEATURES

The ICS8705 is a highly versatile 1:8 Differen- • 8 LVCMOS/LVTTL outputs, 7Ω typical output impedance

ICS

tial-to-LVCMOS/LVTTL Clock Generator and a

• Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs

member of the HiPerClockS™family of High Per-

HiPerClockS™

• CLK1, nCLK1 pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

formance Clock Solutions from ICS.The ICS8705

has two selectable clock inputs. The CLK1,

nCLK1 pair can accept most standard differential input lev-

els.The single ended CLK0 input accepts LVCMOS or LVTTL

input levels.The ICS8705 has a fully integrated PLL and can

be configured as zero delay buffer, multiplier or divider and

has an input and output frequency range of 15.625MHz to

250MHz.The reference divider, feedback divider and output

divider are each programmable, thereby allowing for the fol-

lowing output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2,

1:4, 1:8. The external feedback allows the device to achieve

“zero delay” between the input clock and the output clocks.

The PLL_SEL pin can be used to bypass the PLL for system

test and debug purposes. In bypass mode, the reference clock

is routed around the PLL and into the internal output dividers.

• CLK0 input accepts LVCMOS or LVTTL input levels

• Output frequency range: 15.625MHz to 250MHz

• Input frequency range: 15.625MHz to 250MHz

• VCO range: 250MHz to 500MHz

• External feedback for “zero delay” clock regeneration

with configurable frequencies

• Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• Fully integrated PLL

• Cycle-to-cycle jitter: 45ps (maximum)

• Output skew: CLK0, 65ps (maximum)

CLK1, nCLK1, 55ps (maximum)

• Static Phase Offset: 25 125ps (maximum), CLK0

• Full 3.3V or 2.5V operating supply

• Lead-Free package available

• Industrial temperature information available upon request

BLOCK DIAGRAM

PIN ASSIGNMENT

PLL_SEL

÷2, ÷4, ÷8, ÷16,

÷32, ÷64, ÷128

CLK0

32 31 30 29 28 27 26 25

SEL0

SEL1

VDDO

CLK1

nCLK1

PLL

CLK0

GND

CLK_SEL

FB_IN

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

ICS8705

CLK1

nCLK1

CLK_SEL

V^DDO

GND

10 11 12 13 14 15 16

SEL0

SEL1

SEL2

SEL3

32-Lead LQFP

7mm x 7mm x 1.4 mm

Y Package

Top View

8705BY

www.icst.com/products/hiperclocks.html

REV. G JUNE 16, 2004

12 3 4 5 6 7...17

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与ICS8705BYLFT相关器件

型号	品牌	获取价格	描述	数据表
ICS8705BYT	ICSI	获取价格	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
ICS870S208BK	IDT	获取价格	Low Skew Clock Driver, 870S Series, 4 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.92
ICS870S208BKLF	IDT	获取价格	Low Skew Clock Driver, 870S Series, 4 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.92
ICS870S208BKLFT	IDT	获取价格	Low Skew Clock Driver, 870S Series, 4 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.92
ICS870S208BKT	IDT	获取价格	Low Skew Clock Driver, 870S Series, 4 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.92
ICS871002AGI-02	IDT	获取价格	PLL Based Clock Driver, 871002 Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.5
ICS871002AGI-02LF	IDT	获取价格	PLL Based Clock Driver, 871002 Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.5
ICS871002AGI-02T	IDT	获取价格	PLL Based Clock Driver, 871002 Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.5
ICS871004AGI-04	IDT	获取价格	DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS
ICS871004AGI-04LF	IDT	获取价格	DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS

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