Datasheet > ICS8705AYT

ICS8705AYT

更新时间： 2024-09-29 21:14:59

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
12页	159K
描述
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32

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ICS8705AYT 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	LQFP,	针数：	32
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.26	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e0
长度：	7 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	32	实输出次数：	8
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7 mm
最小 fmax：	15.625 MHz	Base Number Matches：	1

ICS8705AYT 数据手册

PRELIMINARY

ICS8705

Integrated

Circuit

Systems, Inc.

ZERO DELAY DIFFERENTIAL-TO-LVCMOS

C^LOCKGENERATOR

GENERAL DESCRIPTION

FEATURES

The ICS8705 is a highly versatile 1:8 Differen- • Fully integrated PLL

,&6

tial-to-LVCMOS clock generator and a member

of the HiPerClockS™ family of High Performance

Clock Solutions from ICS. The ICS8705 has

two selectable clock inputs. The CLK1, nCLK1

• 8 LVCMOS outputs, 7Ω typical output impedance

HiPerClockS™

• Selectable CLK1, nCLK1 or LVCMOS clock inputs

• CLK1, nCLK1 pair can accept the following differential input

levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

pair can accept most standard differential input levels. The

single ended CLK0 input accpets LVCMOS or LVTTL input

levels.The ICS8705 has a fully integrated PLL and can be

configured as zero delay buffer, multiplier or divider and has

an input and output frequency range of 15.625MHz to 350MHz.

The reference divider, feedback divider and output divider are

each programmable, thereby allowing for the following out-

put-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8.

The external feedback allows the device to achieve “zero de-

lay” between the input clock and the output clocks. The

PLL_SEL pin can be used to bypass the PLL for system test

and debug purposes. In bypass mode, the reference clock is

routed around the PLL and into the internal output dividers.

• CLK0 input accepts LVCMOS or LVTTL input levels

• Output frequency range: 15.625MHz - 350MHz

• Input frequency range: 15.625MHz - 350MHz

• VCO range: 250MHz - 700MHz

• External feedback for “zero delay” clock regeneration with

configurable frequencies

• Programmable dividers allow for the following output-to-

input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• Cycle-to-cycle jitter: 24ps (typical)

• Output skew: 60ps (typical)

• PLL reference zero delay: TBD

• 3.3V supply voltage

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

BLOCK DIAGRAM

PIN ASSIGNMENT

PLL_SEL

CLK0

32 31 30 29 28 27 26 25

CLK1

nCLK1

SEL0

SEL1

VDDO

PLL

CLK_SEL

CLK0

GND

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

FB_IN

ICS8705

CLK1

V^DDO

nCLK1

CLK_SEL

GND

10 11 12 13 14 15 16

SEL0

SEL1

SEL2

SEL3

32-Lead LQFP

7mm x 7mm x 1.4 mm

Y Package

Top View

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

8705AY

www.icst.com/products/hiperclocks.html

REV. A SEPTEMBER 26, 2001

12 3 4 5 6 7...12

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与ICS8705AYT相关器件

型号	品牌	获取价格	描述	数据表
ICS8705BY	ICSI	获取价格	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
ICS8705BYI	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS8705BYILF	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS8705BYIT	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS8705BYLF	ICSI	获取价格	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
ICS8705BYLFT	ICSI	获取价格	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
ICS8705BYT	ICSI	获取价格	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
ICS870S208BK	IDT	获取价格	Low Skew Clock Driver, 870S Series, 4 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.92
ICS870S208BKLF	IDT	获取价格	Low Skew Clock Driver, 870S Series, 4 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.92
ICS870S208BKLFT	IDT	获取价格	Low Skew Clock Driver, 870S Series, 4 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.92

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