Datasheet > ICS8702BYT

ICS8702BYT

更新时间： 2024-09-26 22:11:35

品牌	Logo	应用领域
矽成 - ICSI		时钟发生器逻辑集成电路输出元件驱动
页数	文件大小	规格书
12页	220K
描述
LOW SKEW ±1, ±2 CLOCK GENERATOR

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中文翻译

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数据手册

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ICS8702BYT 数据手册

Integrated

Circuit

Systems, Inc.

ICS8702

LOW SKEW ¸1, ¸2

C^LOCKGENERATOR

GENERAL DESCRIPTION

FEATURES

The ICS8702 is a very low skew, ÷1, ÷2 Clock 20 LVCMOS outputs, 7Ω typical output impedance

,&6

Generator and a member of the HiPerClockS

Output frequency up to 250 MHz

HiPerClockS™ family of High Performance Clock Solutions

from ICS. The ICS8702 is designed to trans-

150ps bank skew, 200ps output, 250ps multiple frequency

skew, 650ps part-to-part skew

late any differential signal levels to LVCMOS lev-

els. True or inverting, single-ended to LVCMOS translation

can be achieved with a resistor bias on the nCLK or CLK

inputs, respectively. The effective fanout can be increased

from 20 to 40 by utilizing the ability of the outputs to drive two

series terminated lines.

Translates any differential input signal (PECL, HSTL, LVDS)

to LVCMOS levels without external bias networks

Translates any single-ended input signal to LVCMOS levels

with a resistor bias on nCLK input

The divide select inputs, DIV_SELx, control the output fre-

quency of each bank. The outputs can be utilized in the ÷1,

÷2 or a combination of ÷1 and ÷2 modes. The bank enable

inputs, BANK_EN0:1, supports enabling and disabling each

bank of outputs individually. The master reset input, nMR/OE,

resets the internal frequency dividers and also controls the

enabling and disabling of all outputs simultaneously.

Translates any single-ended input signal to inverted LVCMOS

levels with a resistor bias on CLK input

LVCMOS / LVTTLcontrol inputs

Bank enable logic allows unused banks to be disabled

in reduced fanout applications

3.3V or mixed 3.3V input, 2.5V output operating

supply modes

The ICS8702 is characterized at 3.3V and mixed 3.3V input

supply, and 2.5V output supply operating modes. Guaranteed

bank, output, multiple frequency and part-to-part skew char-

acteristics make the ICS8702 ideal for those clock distribu-

tion applications demanding well defined performance and

repeatability.

48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm

package body, 0.5mm package lead pitch

0°C to 70°C ambient operating temperature

Other divide values available on request

BLOCK DIAGRAM

PIN ASSIGNMENT

÷1

÷2

CLK

nCLK

QAO - QA4

QB0 - QB4

QC0 - QC4

QD0 - QD4

48 47 46 45 44 43 42 41 40 39 38 37

QC3

VDDO

QC4

DIV_SELA

DIV_SELB

DIV_SELC

DIV_SELD

QB1

VDDO

QB0

QD0

QA4

VDDO

QD1

VDD0

QA3

ICS8702

GND

QD2

GND

QA2

GND

QD3

GND

QA1

VDDO

QD4

VDDO

QA0

13 14 15 16 17 18 19 20 21 22 23 24

nMR/OE

BANK_EN0

BANK_EN1

Bank Enable

Logic

48-Lead LQFP

Y Package

Top View

8702

www.icst.com

REV. A - AUGUST 7, 2000

12 3 4 5 6 7...12

中文翻译

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与ICS8702BYT相关器件

型号	品牌	获取价格	描述	数据表
ICS8702BY-T	IDT	获取价格	Clock Driver, 8702 Series, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40
ICS8705	IDT	获取价格	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
ICS8705	ICSI	获取价格	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
ICS8705AY	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS8705AYLF	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS8705AYT	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS8705BY	ICSI	获取价格	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
ICS8705BYI	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS8705BYILF	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS8705BYIT	IDT	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM

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