Datasheet > ICS8701ICYILFT

ICS8701ICYILFT

更新时间： 2024-01-12 14:59:33

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
13页	118K
描述
Clock Driver

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

ICS8701ICYILFT 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

ICS8701ICYILFT 数据手册

ICS8701I

Integrated

Circuit

Systems, Inc.

LOW SKEW, ÷1, ÷2

CLOCK GENERATOR

GENERAL DESCRIPTION

FEATURES

he ICS8701I is a low skew, ÷1, ÷2 Clock Gen-

• Twenty LVCMOS outputs, 7Ω typical output impedance

• LVCMOS / LVTTL clock input

ICS

erator and a member of the HiPerClockS™family

HiPerClockS™ of High Performance Clock Solutions from ICS.

The low impedance LVCMOS outputs are de-

signed to drive 50Ω series or parallel terminated

transmission lines.The effective fanout can be increased from

20 to 40 by utilizing the ability of the outputs to drive two se-

ries terminated lines.

• Maximum input frequency: 250MHz

• Bank enable logic allows unused banks to be disabled

in reduced fanout applications

• Bank skew: 200ps

The divide select inputs, DIV_SELx, control the output

frequency of each bank.The outputs can be utilized in the ÷1,

÷2 or a combination of ÷1 and ÷2 modes. The bank enable

inputs, BANK_EN0:1, support enabling and disabling each

bank of outputs individually.The master reset input, nMR/OE,

resets the internal frequency dividers and also controls the

active and high impedance states of all outputs.

• Output skew: 250ps

• Multiple frequency skew: 300ps

• Part-to-part skew: 600ps

• 3.3V or mixed 3.3V input, 2.5V output operating supply

• -40°C to 85°C ambient operating temperature

• Other divide values available on request

The ICS8701I is characterized at 3.3V and mixed 3.3V input

supply, and 2.5V output supply operating modes. Guaranteed

bank, output and part-to-part skew characteristics make the

ICS8701I ideal for those clock distribution applications de-

manding well defined performance and repeatability.

• Available in both standard and lead-free RoHS compliant

packages

BLOCK DIAGRAM

PIN ASSIGNMENT

÷1

CLK

QA0:QA4

÷2

48 47 46 45 44 43 42 41 40 39 38 37

DIV_SELA

DIV_SELB

DIV_SELC

DIV_SELD

QC3

V^DDO

QC4

QD0

V^DDO

QD1

GND

QD2

GND

QD3

V^DDO

QD4

QB1

V^DDO

QB0

QA4

V^DDO

QA3

GND

QA2

GND

QA1

V^DDO

QA0

QB0:QB4

QC0:QC4

QD0:QD4

ICS8701I

13 14 15 16 17 18 19 20 21 22 23 24

nMR/OE

BANK_EN0

BANK_EN1

Bank Enable

Logic

48-Pin LQFP

7mm x 7mm x 1.4mm package body

Y Package

TopView

8701CYI

www.icst.com/products/hiperclocks.html

REV.B FEBRUARY 28, 2006

12 3 4 5 6 7...13

中文翻译

下载PDF

与ICS8701ICYILFT相关器件

型号	品牌	获取价格	描述	数据表
ICS8701ICYIT	IDT	获取价格	Clock Driver
ICS8702	ICSI	获取价格	LOW SKEW ±1, ±2 CLOCK GENERATOR
ICS87021AMIT	IDT	获取价格	Low Skew Clock Driver, 87021 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X
ICS8702BY	ICSI	获取价格	LOW SKEW ±1, ±2 CLOCK GENERATOR
ICS8702BYLF	IDT	获取价格	Low Skew Clock Driver, 8702 Series, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7
ICS8702BYLFT	IDT	获取价格	Low Skew Clock Driver, 8702 Series, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7
ICS8702BYT	ICSI	获取价格	LOW SKEW ±1, ±2 CLOCK GENERATOR
ICS8702BY-T	IDT	获取价格	Clock Driver, 8702 Series, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40
ICS8705	IDT	获取价格	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
ICS8705	ICSI	获取价格	ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

与ICS8701ICYILFT相关文章

LTM4644/LTM4644-1：创新的四输出同步降压微模块调节器
2024-07-02

2
2N3500：一款多用途NPN硅晶体管的全面解析
2024-07-02

3
最详细资料解析：BA5917AFP参数说明、引脚说明
2024-07-02

5
MAX232IDR数据手册：产品特性、电气参数、替代型号推荐
2024-07-02

3

产品中心

服务支持

精选活动

关于我们

帮助中心

ICS8701ICYILFT

ICS8701ICYILFT 技术参数

ICS8701ICYILFT 数据手册

与ICS8701ICYILFT相关器件

与ICS8701ICYILFT相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ICS8701ICYILFT

ICS8701ICYILFT 技术参数

ICS8701ICYILFT 数据手册

与ICS8701ICYILFT相关器件

与ICS8701ICYILFT相关文章

您还可以找

您在本页遇到什么问题？