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ICS8702BYLF PDF预览

ICS8702BYLF

更新时间： 2024-02-01 21:12:36
品牌 Logo 应用领域
艾迪悌 - IDT 驱动输出元件逻辑集成电路
页数 文件大小 规格书
13页 207K
描述
Low Skew Clock Driver, 8702 Series, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC, LQFP-48

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ICS8702BYLF 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：LFQFP, QFP48,.35SQ,20针数：48
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.19其他特性：ALSO OPERATES AT MIXED 3.3V CORE AND 2.5V OUTPUT SUPPLY
系列：8702输入调节：DIFFERENTIAL
JESD-30 代码：S-PQFP-G48JESD-609代码：e3
长度：7 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
最大I（ol）：0.027 A湿度敏感等级：3
功能数量：1反相输出次数：
端子数量：48实输出次数：20
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP48,.35SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：3.6 ns传播延迟（tpd）：3.6 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.2 ns
座面最大高度：1.6 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：7 mmBase Number Matches：1

ICS8702BYLF 数据手册

 浏览型号ICS8702BYLF的Datasheet PDF文件第2页浏览型号ICS8702BYLF的Datasheet PDF文件第3页浏览型号ICS8702BYLF的Datasheet PDF文件第4页浏览型号ICS8702BYLF的Datasheet PDF文件第5页浏览型号ICS8702BYLF的Datasheet PDF文件第6页浏览型号ICS8702BYLF的Datasheet PDF文件第7页 
ICS8702  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, ÷1, ÷2  
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS8702 is a low skew, ÷1, ÷2 Differential-to- • Twenty LVCMOS outputs, 7Ω typical output impedance  
ICS  
HiPerClockS™  
LVCMOS Clock Generator and a member of the  
• One differential clock input pair  
HiPerClockS™family of High Performance Clock  
Solutions from ICS. The ICS8702 is designed to  
translate any differential signal levels to  
• CLK, nCLK supports the following input types:  
LVDS, LVPECL, LVHSTL, SSTL, HCSL  
LVCMOS/LVTTL levels. True or inverting, single-ended to  
LVCMOS translation can be achieved with a resistor bias  
on the nCLK or CLK inputs, respectively. The effective fan-  
out can be increased from 20 to 40 by utilizing the ability of  
the outputs to drive two series terminated lines.  
• Maximum output frequency: 250MHz  
• Translates any differential input signal (LVPECL, LVHSTL,  
LVDS) to LVCMOS levels without external bias networks  
• Translates any single-ended input signal to LVCMOS levels  
with a resistor bias on nCLK input  
The divide select inputs, DIV_SELx, control the output fre-  
quency of each bank.The outputs can be utilized in the ÷1, ÷2  
or a combination of ÷1 and ÷2 modes. The bank enable in-  
puts, BANK_EN0:1, supports enabling and disabling each  
bank of outputs individually.The master reset input, nMR/OE,  
resets the internal frequency dividers and also controls the  
enabling and disabling of all outputs simultaneously.  
• Bank enable logic allows unused banks to be disabled in  
reduced fanout applications  
•
•
•
•
Output skew: 200ps (maximum)  
Bank skew: 150ps (maximum)  
Part-to-part skew: 650ps (maximum)  
Multiple frequency skew: 250ps (maximum)  
The ICS8702 is characterized at 3.3V and mixed 3.3V input  
supply, and 2.5V output supply operating modes. Guaranteed  
bank, output, multiple frequency and part-to-part skew char-  
acteristics make the ICS8702 ideal for those clock dis-  
tribution applications demanding well defined performance  
and repeatability.  
• 3.3V or mixed 3.3V input, 2.5V output operating  
supply modes  
• 0°C to 70°C ambient operating temperature  
• Other divide values available on request  
• Available in both standard and lead-free RoHS compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
CLK  
nCLK  
÷1  
÷2  
1
0
QA0:QA4  
QB0:QB4  
QC0:QC4  
QD0:QD4  
48 47 46 45 44 43 42 41 40 39 38 37  
QC3  
VDDO  
QC4  
QD0  
VDDO  
QD1  
GND  
QD2  
GND  
QD3  
VDDO  
QD4  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
QB1  
VDDO  
QB0  
QA4  
VDDO  
QA3  
GND  
QA2  
GND  
QA1  
VDDO  
QA0  
DIV_SELA  
DIV_SELB  
DIV_SELC  
DIV_SELD  
2
1
0
3
4
5
6
ICS8702  
7
1
0
8
9
10  
11  
12  
1
0
13 14 15 16 17 18 19 20 21 22 23 24  
nMR/OE  
BANK_EN0  
BANK_EN1  
Bank Enable  
Logic  
48-Lead LQFP  
7mm x 7mm x 1.4mm  
Y Package  
TopView  
8702BY  
www.icst.com/products/hiperclocks.com  
REV. D OCTOBER 28, 2008  
1
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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
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