Datasheet > ICS8701CYIT

ICS8701CYIT

更新时间： 2024-01-17 23:39:33

品牌	Logo	应用领域
矽成 - ICSI		时钟发生器
页数	文件大小	规格书
13页	124K
描述
LOW SKEW ±1, ±2 CLOCK GENERATOR

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技术参数
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ICS8701CYIT 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

ICS8701CYIT 数据手册

ICS8701I

LOW SKEW 1, 2

CLOCK GENERATOR

Integrated

Circuit

Systems, Incꢀ

GENERAL DESCRIPTION

FEATURES

The ICS8701I is a low skew, ÷1, ÷2 Clock Gen-

• 20 LVCMOS outputs, 7 typical output impedance

,&6

erator and a member of the HiPerClockS™

• Output frequency up to 250MHz

HiPerClockS™ family of High Performance Clock Solutions

from ICS. The low impedance LVCMOS out-

• 200ps bank skew, 250ps output skew, 300ps multiple

frequency skew, 600ps part-to-part skew

puts are designed to drive 50 series or par-

allel terminated transmission lines. The effective fanout can

be increased from 20 to 40 by utilizing the ability of the

outputs to drive two series terminated lines.

• LVCMOS / LVTTL clock input

• LVCMOS control inputs

The divide select inputs, DIV_SELx, control the output fre-

quency of each bank. The outputs can be utilized in the ÷1,

÷2 or a combination of ÷1 and ÷2 modes. The bank enable

inputs, BANK_EN0:1, support enabling and disabling each

bank of outputs individually. The master reset input, nMR/

OE, resets the internal frequency dividers and also con-

trols the active and high impedance states of all outputs.

• Bank enable logic allows unused banks to be disabled

in reduced fanout applications

• 3.3V or mixed 3.3V input, 2.5V output operating

supply modes

• 48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm

package body, 0.5mm package lead pitch

The ICS8701I is characterized at 3.3V and mixed 3.3V in-

put supply, and 2.5V output supply operating modes. Guar-

anteed bank, output and part-to-part skew characteristics

make the ICS8701I ideal for those clock distribution appli-

cations demanding well defined performance and repeat-

ability.

• -40°C to 85°C ambient operating temperature

• Other divide values available on request

BLOCK DIAGRAM

PIN ASSIGNMENT

LVCMOS_CLK

QAO - QA4

48 47 46 45 44 43 42 41 40 39 38 37

QC3

VDDO

QC4

DIV_SELA

DIV_SELB

DIV_SELC

DIV_SELD

QB1

VDDO

QB0

QB0 - QB4

QC0 - QC4

QD0 - QD4

QD0

QA4

VDDO

QD1

VDDO

QA3

ICS8701I

GND

QD2

GND

QA2

GND

QD3

GND

QA1

VDDO

QD4

VDDO

QA0

13 14 15 16 17 18 19 20 21 22 23

nMR/OE

BANK_EN0

BANK_EN1

Bank Enable

Logic

48-Pin LQFP

Y Package

Top View

8701I

www.icst.com/products/hiperclocks.html

REV. A MARCH 16, 2001

12 3 4 5 6 7...13

中文翻译

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与ICS8701CYIT相关器件

型号	品牌	获取价格	描述	数据表
ICS8701CYLF	IDT	获取价格	Low Skew Clock Driver, 8701 Series, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7
ICS8701CYLFT	IDT	获取价格	Low Skew Clock Driver, 8701 Series, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7
ICS8701CYT	ICSI	获取价格	LOW SKEW ±1, ±2 CLOCK GENERATOR
ICS8701I	ICSI	获取价格	LOW SKEW ±1, ±2 CLOCK GENERATOR
ICS8701ICYI	IDT	获取价格	Clock Driver
ICS8701ICYILFT	IDT	获取价格	Clock Driver
ICS8701ICYIT	IDT	获取价格	Clock Driver
ICS8702	ICSI	获取价格	LOW SKEW ±1, ±2 CLOCK GENERATOR
ICS87021AMIT	IDT	获取价格	Low Skew Clock Driver, 87021 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X
ICS8702BY	ICSI	获取价格	LOW SKEW ±1, ±2 CLOCK GENERATOR

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