Datasheet > ICS8701CYT

ICS8701CYT

更新时间： 2024-01-24 20:42:49

品牌	Logo	应用领域
矽成 - ICSI		时钟发生器
页数	文件大小	规格书
15页	132K
描述
LOW SKEW ±1, ±2 CLOCK GENERATOR

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技术参数
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ICS8701CYT 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

ICS8701CYT 数据手册

ICS8701

Integrated

Circuit

Systems, Incꢀ

LOW SKEW

÷1, ÷2

CLOCK GENERATOR

GENERAL DESCRIPTION

FEATURES

The ICS8701 is a low skew, ÷1, ÷2 Clock Gen-

• 20 LVCMOS outputs, 7Ω typical output impedance

• 1 LVCMOS clock input

erator and a member of the HiPerClockS™

HiPerClockS™ family of High Performance Clock Solutions

from ICS. The low impedance LVCMOS out-

• Maximum output frequency up to 250MHz

puts are designed to drive 50Ω series or par-

• Bank enable logic allows unused banks to be disabled

in reduced fanout applications

allel terminated transmission lines. The effective fanout can

be increased from 20 to 40 by utilizing the ability of the

outputs to drive two series terminated lines.

• Output skew: 250ps (maximum)

The divide select inputs, DIV_SELx, control the output fre-

quency of each bank. The outputs can be utilized in the ÷1,

÷2 or a combination of ÷1 and ÷2 modes. The bank enable

inputs, BANK_EN0:1, support enabling and disabling each

bank of outputs individually. The master reset input, nMR/

OE, resets the internal frequency dividers and also con-

trols the active and high impedance states of all outputs.

• Part-to-part skew: 600ps (maximum)

• Bank skew: 200ps (maximum)

• Multiple frequency skew: 300ps (maximum)

• 3.3V or mixed 3.3V input, 2.5V output operating

supply modes

• 0°C to 70°C ambient operating temperature

• Other divide values available on request

The ICS8701 is characterized at 3.3V and mixed 3.3V input

supply, and 2.5V output supply operating modes. Guaranteed

bank, output and part-to-part skew characteristics make the

ICS8701 ideal for those clock distribution applications de-

manding well defined performance and repeatability.

BLOCK DIAGRAM

PIN ASSIGNMENT

÷1

CLK

QAO - QA4

÷2

48 47 46 45 44 43 42 41 40 39 38 37

QC3

VDDO

QC4

QD0

VDDO

QD1

GND

QD2

GND

QD3

V^DDO

QD4

QB1

V^DDO

QB0

QA4

V^DDO

QA3

GND

QA2

GND

QA1

V^DDO

QA0

DIV_SELA

DIV_SELB

DIV_SELC

DIV_SELD

QB0 - QB4

QC0 - QC4

QD0 - QD4

ICS8701

13 14 15 16 17 18 19 20 21 22 23 24

nMR/OE

BANK_EN0

BANK_EN1

Bank Enable

Logic

48-Pin LQFP

7mm x 7mm x 1.4mm

Y Package

Top View

8701CY

www.icst.com/products/hiperclocks.html

REV. B AUGUST 2, 2001

12 3 4 5 6 7...15

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与ICS8701CYT相关器件

型号	品牌	获取价格	描述	数据表
ICS8701I	ICSI	获取价格	LOW SKEW ±1, ±2 CLOCK GENERATOR
ICS8701ICYI	IDT	获取价格	Clock Driver
ICS8701ICYILFT	IDT	获取价格	Clock Driver
ICS8701ICYIT	IDT	获取价格	Clock Driver
ICS8702	ICSI	获取价格	LOW SKEW ±1, ±2 CLOCK GENERATOR
ICS87021AMIT	IDT	获取价格	Low Skew Clock Driver, 87021 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X
ICS8702BY	ICSI	获取价格	LOW SKEW ±1, ±2 CLOCK GENERATOR
ICS8702BYLF	IDT	获取价格	Low Skew Clock Driver, 8702 Series, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7
ICS8702BYLFT	IDT	获取价格	Low Skew Clock Driver, 8702 Series, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7
ICS8702BYT	ICSI	获取价格	LOW SKEW ±1, ±2 CLOCK GENERATOR

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