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ICS84314AYT PDF预览

ICS84314AYT

更新时间: 2024-11-02 22:36:07
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
18页 222K
描述
350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER

ICS84314AYT 数据手册

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ICS84314  
Integrated  
Circuit  
Systems, Inc.  
350MH  
Z
, CRYSTAL  
-
TO-3.3V/2.5V LVPECL  
F
REQUENCY  
S
YNTHESIZER W/FANOUT  
BUFFER  
FEATURES  
GENERAL DESCRIPTION  
Fully integrated PLL  
4 differential 3.3V or 2.5V LVPECL outputs  
The ICS84314 is a general purpose quad output  
ICS  
frequency synthesizer and a member of the  
HiPerClockS™ family of High Performance Clock  
HiPerClockS™  
Solutions from ICS. When the device uses par- Selectable crystal oscillator interface  
allel loading, the M bits are programmable and  
or LVCMOSTEST_CLK input  
the output divider is hard-wired for divide by 2 thus providing  
a frequency range of 125MHz to 350MHz. In serial program-  
ming mode, the M bits are programmable and the output di-  
vider can be set for either divide by 2 or divide by 4, providing  
a frequency range of 62.5MHz to 350MHz. The low cycle-  
cycle jitter and broad frequency range of the ICS84314 make  
it an ideal clock generator for a variety of demanding applica-  
tions which require high performance.  
Output frequency range: 62.5MHz to 350MHz  
VCO range: 250MHz to 700MHz  
Parallel interface for programming counter  
and output dividers during power-up  
Serial 3 wire interface  
Cycle-to-cycle jitter: 23ps (typical)  
Output skew: 16ps (typical)  
Output duty cycle: 49% < odc < 51%, fout 125MHz  
Full 3.3V or mixed 3.3V core, 2.5V operating supply  
0°C to 85°C ambient operating temperature  
Lead-Free package available  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VCO_SEL  
XTAL_SEL  
32 31 30 29 28 27 26 25  
M4  
M5  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
TEST_CLK  
XTAL_SEL  
VCCA  
TEST_CLK  
0
M6  
XTAL1  
1
OSC  
M7  
S_LOAD  
S_DATA  
S_CLOCK  
MR  
XTAL2  
ICS84314  
M8  
÷ 16  
VEE  
VCC  
VCCO  
VCCO  
PLL  
Q0  
nQ0  
PHASE DETECTOR  
9
10 11 12 13 14 15 16  
Q1  
nQ1  
MR  
0
VCO  
÷2  
÷4  
Q2  
nQ2  
÷ M  
1
÷2  
Q3  
nQ3  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
S_LOAD  
S_DATA  
S_CLOCK  
Y Package  
TopView  
CONFIGURATION  
INTERFACE  
LOGIC  
nP_LOAD  
M0:M8  
84314AY  
www.icst.com/products/hiperclocks.html  
REV. C JANUARY 27, 2005  
1

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