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ICS8431CM-01T PDF预览

ICS8431CM-01T

更新时间: 2024-11-02 22:09:35
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
11页 2085K
描述
200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER

ICS8431CM-01T 数据手册

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ICS8431-01  
200MHZ, LOW JITTER,  
LVPECLFREQUENCY SYNTHESIZER  
Integrated  
Circuit  
Systems, Incꢀ  
GENERAL DESCRIPTION  
FEATURES  
The ICS8431-01 is a general purpose clock Fully integrated PLL  
,&6  
frequency synthesizer for IA64/32 application and  
Differential 3.3V LVPECLoutput  
HiPerClockS™  
a member of the HiPerClockS™ family of High  
Performance Clock Solutions from ICS. The  
ICS8431-01 consists of one independent low  
200MHz output frequency  
48% to 52% duty cycle  
Crystal oscillator interface  
bandwidth PLL timing channel. A 16.666MHz crystal is used  
as the input to the on-chip oscillator. The M is configured to  
produce a fixed output frequency of 200MHz.  
Spread Spectrum Clocking (SSC) fixed at 1/2% modulation  
for environments requiring ultra low EMI. Typical10dB EMI  
reduction can be achieved with spread spectrum modulation  
Programmable features of the ICS8431-01 support four  
operational modes. The four modes are spread spectrum  
clocking (SSC), non-spread spectrum clock and two test  
modes which are controlled by the SSC_CTL[1:0] pins. Un-  
like other synthesizers, the ICS8431-01 can immediately  
change spread-spectrum operation without having to reset  
the device.  
LVTTL/ LVCMOS control inputs  
PLL bypass modes supporting in-circuit testing and on-chip  
functional block characterization  
28 lead SOIC  
In SSC mode, the output clock is modulated in order to  
achieve a reduction in EMI. In one of the PLL bypass test  
modes, the PLL is disconnected as the source to the  
differential output allowing an external source to be  
connnected to the TEST_I/O pin. This is useful for in-  
circuit testing and allows the differential output to be driven  
at a lower frequency throughout the system clock tree. In the  
other PLL bypass mode, the oscillator divider is used as the  
source to both the M and the Fout divide by 2. This is useful  
for characterizing the oscillator and internal dividers.  
RMS cycle-to-cycle jitter of 2ps  
Typical cycle-to-cycle jitter of 18ps  
0° to 85°C ambiant operating temperature  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
nc  
nc  
nc  
nc  
1
2
3
4
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
nc  
XTAL1  
OSC  
VDDI  
XTAL2  
XTAL1  
nc  
nc  
VDDA  
VEE  
XTAL2  
÷ 16  
nc  
nc  
nc  
nc  
nc  
5
6
7
8
PLL  
9
RESERVED  
nc  
PHASE  
DETECTOR  
SSC_CTL0  
SSC_CTL1  
VEE  
TEST_I/O  
VDD  
10  
11  
12  
13  
14  
VDDO  
FOUT  
nFOUT  
VEE  
VCO  
÷ 2  
FOUT  
nFOUT  
÷ M  
ICS8431-01  
28-Lead SOIC  
M Package  
TEST_I/O  
SSC_CTL0  
SSC  
Top View  
Control  
SSC_CTL1  
Logic  
ICS8431CM-01  
www.icst.com/products/hiperclocks.html  
REV. A JUNE 5, 2001  
1

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