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ICS8431EMI-01 PDF预览

ICS8431EMI-01

更新时间: 2024-11-04 04:32:43
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
15页 328K
描述
Clock Generator, 200MHz, PDSO28, 7.50 X 18.05 MM, 2.25 MM, MS-013, MO-119, SOIC-28

ICS8431EMI-01 数据手册

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ICS8431I-01  
200MHZ, LOW JITTER,  
CRYSTAL OSCILLATOR-TO-3.3V LVPECLFREQUENCY SYNTHESIZER  
Integrated  
Circuit  
Systems, Incꢀ  
GENERAL DESCRIPTION  
FEATURES  
The ICS8431I-01 is a general purpose clock Fully integrated PLL  
frequency synthesizer for IA64/32 applications  
Differential 3.3V LVPECLoutput  
HiPerClockS™  
and a member of the HiPerClockS™ family of High  
Performance Clock Solutions from ICS. The  
ICS8431I-01 consists of one independent low  
Crystal oscillator interface  
Output frequency of 200MHz  
48% to 52% duty cycle  
bandwidth PLL timing channel. A 16.666MHz crystal is used  
as the input to the on-chip oscillator. The M divide is config-  
ured to produce a fixed output frequency of 200MHz.  
Spread Spectrum Clocking (SSC) fixed at 1/2% modulation  
for environments requiring ultra low EMI. Typical10dB EMI  
reduction can be achieved with spread spectrum modulation  
Programmable features of the ICS8431I-01 support four  
operational modes. The four modes are spread spectrum  
clocking (SSC), non-spread spectrum clocking and two test  
modes which are controlled by the SSC_CTL[1:0] pins. Un-  
like other synthesizers, the ICS8431I-01 can immediately  
change spread-spectrum operation without having to reset  
the device.  
PLLbypass modes supporting in-circuit testing and on-chip  
functional block characterization  
Cycle-to-cycle jitter: 25ps (maximum)  
3.3V supply voltage  
In SSC mode, the output clock is modulated in order to  
achieve a reduction in EMI. In one of the PLL bypass test  
modes, the PLL is disconnected as the source to the  
differential output allowing an external source to be  
connnected to the TEST_I/O pin. This is useful for in-  
circuit testing and allows the differential output to be driven  
at a lower frequency throughout the system clock tree. In the  
other PLL bypass mode, the oscillator divider is used as the  
source to both the M divide and the Fout divide by 2. This is  
useful for characterizing the oscillator and internal dividers.  
-40° to 85°C ambient operating temperature  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
nc  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
nc  
XTAL1  
OSC  
nc  
nc  
2
3
VCC  
XTAL2  
XTAL1  
nc  
XTAL2  
nc  
nc  
4
5
÷ 16  
nc  
nc  
6
7
nc  
VCCA  
VEE  
nc  
8
PLL  
nc  
9
RESERVED  
nc  
PHASE  
DETECTOR  
SSC_CTL0  
SSC_CTL1  
VEE  
10  
11  
12  
13  
14  
VCCO  
FOUT  
nFOUT  
VEE  
VCO  
÷ 2  
TEST_I/O  
VCC  
FOUT  
nFOUT  
÷ M  
ICS8431I-01  
TEST_I/O  
28-Lead SOIC  
7.5mm x 18.05mm x 2.25mm package body  
SSC_CTL0  
SSC  
M Package  
Top View  
Control  
SSC_CTL1  
Logic  
8431EMI-01  
www.icst.com/products/hiperclocks.html  
REV. A FEBRUARY 4, 2003  
1

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