ICS84320I-01
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS84320I-01 is a general purpose, dual • Dual differential 3.3V LVPECL outputs
ICS
HiPerClockS™
output Crystal-to-3.3V Differential LVPECL
High Frequency Synthesizer and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS84320I-01
• Selectable crystal oscillator interface
or LVCMOS/LVTTLTEST_CLK
• Output frequency range: 77.5MHz to 780MHz
• Crystal input frequency range: 14MHz to 40MHz
• VCO range: 620MHz to 780MHz
has a selectable TEST_CLK or crystal inputs. The VCO
operates at a frequency range of 620MHz to 780MHz. The
VCO frequency is programmed in steps equal to the
value of the input reference or crystal frequency. The VCO
and output frequency can be programmed using the
serial or parallel interfaces to the configuration logic. The
low phase noise characteristics of the ICS84320I-01
make it an ideal clock source for 10 Gigabit Ethernet,
SONET, and Serial Attached SCSI applications.
• Parallel or serial interface for programming counter
and output dividers
• Duty cycle: 44% - 56% (N > 1)
• RMS period jitter: 2.0ps (typical)
• RMS phase jitter at 155.52MHz, using a 38.88MHz crystal
(12kHz to 20MHz): 2.38ps (typical)
• RMS phase noise at 155.52MHz (typical)
Offset
Noise Power
100Hz ................ -90.5 dBc/Hz
1kHz ............... -114.2 dBc/Hz
10kHz ............... -123.6 dBc/Hz
100kHz ............... -128.1 dBc/Hz
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in both, Standard and RoHS/Lead-Free
compliant packages
BLOCK DIAGRAM
VCO_SEL
PIN ASSIGNMENT
XTAL_SEL
TEST_CLK
0
XTAL_IN
1
OSC
XTAL_OUT
32 31 30 29 28 27 26 25
M5
M6
M7
M8
N0
N1
nc
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL_OUT
TEST_CLK
XTAL_SEL
VCCA
PLL
ICS84320I-01
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
÷ N
PHASE DETECTOR
÷ 1
÷ 2
÷ 4
÷ 8
MR
0
1
S_LOAD
S_DATA
S_CLOCK
MR
VCO
FOUT0
nFOUT0
FOUT1
nFOUT1
÷ M
Top View
VEE
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
CONFIGURATION
INTERFACE
LOGIC
9
10 11 12 13 14 15 16
TEST
M0:M8
N0:N1
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84320AYI-01
www.icst.com/products/hiperclocks.html
REV.A AUGUST 11, 2005
1