PRELIMINARY
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
350MHZ FREQUENCY MARGINING SYNTHESIZER
ICS843207-350
GENERAL DESCRIPTION
FEATURES
• Seven independently configurable LVPECL outputs at
87.5MHz, 175MHz or 350MHz
The ICS843207-350 is a low phase-noise
ICS
HiPerClockS™
frequency margining synthesizer that targets
clocking for high performance interfaces such
as SPI4.2 and is a member of the HiPerClockS™
family of high performance clock solutions from
• Individual tri-state control of each output
• Selectable crystal oscillator interface designed for 14MHz,
18pF parallel resonant crystal or LVCMOS single-ended input
IDT. In the default mode, the each output can be configured
individually to generate an 87.5MHz, 175MHZ or 350MHz
LVPECL output clock signal from a 14MHz crystal input.
There is also a frequency margining mode available where
the device can be configured, using control pins, to vary
the output frequency up or down from nominal by 5%. The
ICS843207-350 is provided in a 48-pin LQFP package.
• Output frequency can be varied 5% from nominal
• VCO range: 620MHz - 750MHz
• RMS phase jitter @ 350MHz, using a 14MHz crystal
(12kHz - 20MHz): 1.29ps (typical)
• Full 3.3V output supply mode
• 0°C to 70°C ambient operating temperature
PIN ASSIGNMENT
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
48 47 46 45 44 43 42 41 40 39 38 37
1
VCCA
VCC
VCCO
nQ6
Q6
VCCO
Q0
36
35
34
33
2
Q0
00 HiZ
01 ÷2
10 ÷8
11 ÷4
nQ0
Q1
3
BLOCK DIAGRAM
ICS843207-350
4
nQ0
nQ1
VEE
VCCO
Q2
5
32
31
30
48-Pin LQFP
7mm x 7mm x 1.4mm
package body
Y Package
Pullup
Pullup
Pullup
Pullup
2
2
SEL[1:0]
VEE
6
7
VCCO
nQ5
Q5
Q1
00 HiZ
01 ÷2
10 ÷8
11 ÷4
8
29
28
27
Top View
nQ2
Q3
9
nQ1
10
11
12
nQ4
Q4
nQ3
VCCO
SEL[3:2]
26
25
VCCO
13 14 15 16 17 18 19 20 21 22 23 24
Q2
00 HiZ
01 ÷2
10 ÷8
11 ÷4
nQ2
2
2
2
SEL[5:4]
Pulldown
nPLL_SEL
XTAL_IN
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Q3
14MHz
1
0
nQ3
OSC
0
1
SEL[7:6]
Phase
Detector
Predivider
÷2
VCO
XTAL_OUT
REF_CLK
620 - 750MHz
Q4
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pulldown
nQ4
Pulldown
Pullup
Pullup
Pullup
nXTAL_SEL
÷100
(÷95, ÷105)
SEL[9:8]
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Q5
nQ5
Pulldown
Pulldown
Pulldown
MODE
2
SEL[11:10]
MARGIN
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Q6
To O/P Dividers
MR
nQ6
2
SEL[13:12]
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
1
ICS843207AY-350 REV A OCTOBER 19, 2006