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ICS8432-111 PDF预览

ICS8432-111

更新时间: 2024-11-03 11:14:39
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
17页 278K
描述
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

ICS8432-111 数据手册

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ICS8432-111  
Integrated  
Circuit  
Systems, Inc.  
700MH  
Z
/350MH  
Z
D
IFFERENTIAL  
-
TO-3.3V LVPECL FREQUENCY  
SYNTHESIZER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8432-111 is a general purpose, dual out- Dual differential 3.3V LVPECL outputs  
ICS  
put Differential-to-3.3V LVPECL High Frequency  
Selectable differential CLK, nCLK pair or LVCMOSTEST_CLK  
HiPerClockS™  
Synthesizer and a member of the HiPerClockS™  
family of High Performance Clocks Solutions  
from ICS. The ICS8432-111 has a selectable  
CLK, nCLK pair can accept the following differential input  
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL  
differential CLK, nCLK pair or LVCMOS/LVTTLTEST_CLK.The  
TEST_CLK input accepts LVCMOS or LVTTL input levels  
and translates them to 3.3V LVPECL levels. The CLK, nCLK  
pair can accept most standard differential input levels.The  
VCO operates at a frequency range of 200MHz to 700MHz.  
The VCO frequency is programmed in steps equal to the value  
of the input differential or single ended reference frequency.  
Output frequencies up to 700MHz for FOUT and 350MHz for  
FOUT/2 can be programmed using the serial or parallel  
interfaces to the configuration logic. The low phase noise  
characteristics and the multiple frequency outputs of the  
ICS8432-111 makes it an ideal clock source for Fibre Channel  
1 and 2, and Infiniband applications.  
TEST_CLK can accept the following input types:  
LVCMOS or LVTTL  
Maximum FOUT frequency: 700MHz  
Maximum FOUT/2 frequency: 350MHz  
CLK, nCLK or TEST_CLK input frequency: 40MHz  
VCO range: 250MHz to 700MHz  
Parallel or serial interface for programming counter  
andVCO frequency multiplier and dividers  
RMS period jitter: 5ps (maximum)  
Cycle-to-cycle jitter: 40ps (maximum)  
3.3V supply voltage  
0°C to 70°C ambient operating temperature  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VCO_SEL  
CLK_SEL  
TEST_CLK  
0
1
32 31 30 29 28 27 26 25  
CLK  
nCLK  
M5  
M6  
M7  
M8  
N0  
N1  
nc  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
CLK  
TEST_CLK  
CLK_SEL  
VCCA  
ICS8432-111  
10 11 12 13 14 15 16  
32-Lead LQFP  
S_LOAD  
S_DATA  
S_CLOCK  
MR  
PLL  
PHASE DETECTOR  
÷1  
÷2  
÷4  
÷8  
MR  
0
1
VEE  
VCO  
FOUT  
nFOUT  
FOUT/2  
nFOUT/2  
9
÷M  
÷2  
S_LOAD  
S_DATA  
S_CLOCK  
nP_LOAD  
CONFIGURATION  
INTERFACE  
LOGIC  
TEST  
7mm x 7mm x 1.4mm package body  
M0:M8  
N0:N1  
Y Package  
TopView  
8432CY-111  
www.icst.com/products/hiperclocks.html  
REV. B MARCH 3, 2004  
1

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