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ICS8431EM-11T PDF预览

ICS8431EM-11T

更新时间: 2024-11-03 14:36:55
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
18页 2127K
描述
Clock Generator, 255MHz, PDSO28, 7.50 X 18.05 MM, 2.25 MM HEIGHT, MS-013, MO-119, SOIC-28

ICS8431EM-11T 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:7.50 X 18.05 MM, 2.25 MM HEIGHT, MS-013, MO-119, SOIC-28针数:28
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.88
Is Samacsys:NJESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:18.05 mm
端子数量:28最高工作温度:85 °C
最低工作温度:最大输出时钟频率:255 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP28,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V主时钟/晶体标称频率:20 MHz
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Clock Generators最大压摆率:140 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

ICS8431EM-11T 数据手册

 浏览型号ICS8431EM-11T的Datasheet PDF文件第2页浏览型号ICS8431EM-11T的Datasheet PDF文件第3页浏览型号ICS8431EM-11T的Datasheet PDF文件第4页浏览型号ICS8431EM-11T的Datasheet PDF文件第5页浏览型号ICS8431EM-11T的Datasheet PDF文件第6页浏览型号ICS8431EM-11T的Datasheet PDF文件第7页 
ICS8431-11  
255MHZ, LOW JITTER, CRYSTAL OSCILLATOR-  
TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
Integrated  
Circuit  
Systems, Incꢀ  
GENERAL DESCRIPTION  
FEATURES  
Fully integrated PLL  
The ICS8431-11 is a general purpose clock  
frequency synthesizer for IA64/32 application and  
a member of the HiPerClockS™ family of High  
Performance Clock Solutions from ICS. The VCO  
operates at a frequency range of 190MHz to  
Differential 3.3V LVPECLoutput  
HiPerClockS™  
Crystal oscillator interface  
Output frequency range: 95MHz to 255MHz  
Crystal input frequency range: 14MHz to 20MHz  
VCO range: 190MHz to 510MHz  
510MHz providing an output frequency range of 95MHz to  
255MHz. The output frequency can be programmed using the  
parallel interface, M0 thru M8, to the configuration logic.  
Spread spectrum clocking is programmed via the control  
inputs SSC_CTL0 and SSC_CTL1.  
Programmable PLL loop divider for generating a variety  
of output frequencies  
Programmable features of the ICS8431-11 support four  
operational modes. The four modes are spread spectrum  
clocking (SSC), non-spread spectrum clock and two test  
modes which are controlled by the SSC_CTL[1:0] pins. Un-  
like other synthesizers, the ICS8431-11 can immediately  
change spread-spectrum operation without having to reset  
the device.  
Spread Spectrum Clocking (SSC) fixed at 1/2% modulation  
for environments requiring ultra low EMI  
PLL bypass modes supporting in-circuit testing and on-chip  
functional block characterization  
Cycle-to-cycle jitter: 30ps (maximum)  
3.3V supply voltage  
In SSC mode, the output clock is modulated in order to  
achieve a reduction in EMI. In one of the PLL bypass test  
modes, the PLL is disconnected as the source to the  
differential output allowing an external source to be  
connnected to the TEST_I/O pin. This is useful for in-  
circuit testing and allows the differential output to be driven  
at a lower frequency throughout the system clock tree. In the  
other PLL bypass mode, the oscillator divider is used as the  
source to both the M and the Fout divide by 2. This is useful  
for characterizing the oscillator and internal dividers.  
0°C to 85°C ambient operating temperature  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
M0  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
nP_LOAD  
VCC  
XTAL2  
XTAL1  
nc  
XTAL1  
OSC  
M1  
M2  
2
3
XTAL2  
M3  
4
M4  
M5  
5
6
÷ 16  
nc  
M6  
M7  
7
8
VCCA  
VEE  
PLL  
M8  
9
MR  
nc  
PHASE  
DETECTOR  
SSC_CTL0  
SSC_CTL1  
VEE  
TEST_I/O  
VCC  
10  
11  
12  
13  
14  
VCCO  
FOUT  
nFOUT  
VEE  
VCO  
÷ 2  
FOUT  
nFOUT  
÷ M  
ICS8431-11  
28-Lead SOIC  
7.5mm x 18.05mm x 2.25mm package body  
TEST_I/O  
M Package  
Top View  
SSC  
Control  
Logic  
Configuration  
Logic  
M0:M8  
nP_LOAD  
SSC_CTL0  
SSC_CTL1  
8431EM-11  
www.icst.com/products/hiperclocks.html  
REV. B SEPTEMBER 11, 2002  
1

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