Datasheet > ICS8431CM-11T

ICS8431CM-11T

更新时间： 2024-11-02 22:09:35

品牌	Logo	应用领域
矽成 - ICSI		晶体外围集成电路光电二极管时钟
页数	文件大小	规格书
13页	2096K
描述
255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER

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中文翻译

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数据手册

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ICS8431CM-11T 数据手册

ICS8431-11

255MHZ, LOW JITTER,

Integrated

Circuit

Systems, Incꢀ

LVPECLF^REQUENCYSYNTHESIZER

GENERAL DESCRIPTION

FEATURES

• Fully integrated PLL

The ICS8431-11 is a general purpose clock

frequency synthesizer for IA64/32 application and

a member of the HiPerClockS™ family of High

Performance Clock Solutions from ICS. The VCO

operates at a frequency range of 190MHz to

• Differential 3.3V LVPECLoutput

HiPerClockS™

• Programmable PLL loop divider for generating a variety of

output frequencies.

510MHz providing an output frequency range of 95MHz to

255MHz. The output frequency can be programmed using the

parallel interface, M0 thru M8, to the configuration logic.

Spread spectrum clocking is programmed via the control

inputs SSC_CTL0 and SSC_CTL1.

• Crystal oscillator interface

• Spread Spectrum Clocking (SSC) fixed at 1/2% modulation

for environments requiring ultra low EMI

• Typical RMS cycle-to-cycle jitter 2.6 ps

• LVTTL / LVCMOS control inputs

Programmable features of the ICS8431-11 support four

operational modes. The four modes are spread spectrum

clocking (SSC), non-spread spectrum clock and two test

modes which are controlled by the SSC_CTL[1:0] pins. Un-

like other synthesizers, the ICS8431-11 can immediately

change spread-spectrum operation without having to reset

the device.

• PLL bypass modes supporting in-circuit testing and on-chip

functional block characterization

• 3.3V supply voltage

• 28 lead SOIC

• 0°C to 85°C ambient operating temperature

In SSC mode, the output clock is modulated in order to

achieve a reduction in EMI. In one of the PLL bypass test

modes, the PLL is disconnected as the source to the

differential output allowing an external source to be

connnected to the TEST_I/O pin. This is useful for in-

circuit testing and allows the differential output to be driven

at a lower frequency throughout the system clock tree. In the

other PLL bypass mode, the oscillator divider is used as the

source to both the M and the Fout divide by 2. This is useful

for characterizing the oscillator and internal dividers.

BLOCK DIAGRAM

PIN ASSIGNMENT

nP_LOAD

VDDI

XTAL2

XTAL1

OSC

XTAL2

÷ 16

VDDA

VEE

PLL

PHASE

DETECTOR

SSC_CTL0

SSC_CTL1

VEE

TEST_I/O

VDD

VDDO

FOUT

nFOUT

VEE

VCO

÷ 2

FOUT

nFOUT

÷ M

ICS8431-11

28-Lead SOIC

M Package

TEST_I/O

Top View

SSC

Control

Logic

Configuration

Logic

M0:M8

nP_LOAD

SSC_CTL0 SSC_CTL1

ICS8431CM-11

www.icst.com/products/hiperclocks.html

REV. A JULY 11, 2001

12 3 4 5 6 7...13

中文翻译

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与ICS8431CM-11T相关器件

型号	品牌	获取价格	描述	数据表
ICS8431DMI-01	IDT	获取价格	Clock Generator, 200MHz, PDSO28, 7.50 X 18.05 X 2.25 MM, MS-013, MO-119, SOIC-28
ICS8431DMI-01LF	IDT	获取价格	Clock Generator, 200MHz, PDSO28, 7.50 X 18.05 X 2.25 MM, MS-013, MO-119, SOIC-28
ICS8431DMI-01LFT	IDT	获取价格	Clock Generator, 200MHz, PDSO28, 7.50 X 18.05 X 2.25 MM, MS-013, MO-119, SOIC-28
ICS8431DMI-01T	IDT	获取价格	Clock Generator, 200MHz, PDSO28, 7.50 X 18.05 X 2.25 MM, MS-013, MO-119, SOIC-28
ICS8431EM-01LF	IDT	获取价格	Clock Generator, 200MHz, PDSO28, 7.50 X 18.05 MM, 2.25 MM, MS-013, MO-119, SOIC-28
ICS8431EM-01LFT	IDT	获取价格	Clock Generator, 200MHz, PDSO28, 7.50 X 18.05 MM, 2.25 MM, MS-013, MO-119, SOIC-28
ICS8431EM-11LF	IDT	获取价格	Clock Generator, 255MHz, PDSO28, 7.50 X 18.05 MM, 2.25 MM HEIGHT, LEAD FREE, MS-013, MO-11
ICS8431EM-11LFT	IDT	获取价格	Clock Generator, 255MHz, PDSO28, 7.50 X 18.05 MM, 2.25 MM HEIGHT, LEAD FREE, MS-013, MO-11
ICS8431EM-11T	IDT	获取价格	Clock Generator, 255MHz, PDSO28, 7.50 X 18.05 MM, 2.25 MM HEIGHT, MS-013, MO-119, SOIC-28
ICS8431EMI-01	IDT	获取价格	Clock Generator, 200MHz, PDSO28, 7.50 X 18.05 MM, 2.25 MM, MS-013, MO-119, SOIC-28

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