Datasheet > ICS8431CM-01

ICS8431CM-01

更新时间： 2024-11-02 22:09:35

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
11页	2085K
描述
200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ICS8431CM-01 数据手册

ICS8431-01

200MHZ, LOW JITTER,

LVPECLFREQUENCY SYNTHESIZER

Integrated

Circuit

Systems, Incꢀ

GENERAL DESCRIPTION

FEATURES

The ICS8431-01 is a general purpose clock • Fully integrated PLL

,&6

frequency synthesizer for IA64/32 application and

• Differential 3.3V LVPECLoutput

HiPerClockS™

a member of the HiPerClockS™ family of High

Performance Clock Solutions from ICS. The

ICS8431-01 consists of one independent low

• 200MHz output frequency

• 48% to 52% duty cycle

• Crystal oscillator interface

bandwidth PLL timing channel. A 16.666MHz crystal is used

as the input to the on-chip oscillator. The M is configured to

produce a fixed output frequency of 200MHz.

• Spread Spectrum Clocking (SSC) fixed at 1/2% modulation

for environments requiring ultra low EMI. Typical10dB EMI

reduction can be achieved with spread spectrum modulation

Programmable features of the ICS8431-01 support four

operational modes. The four modes are spread spectrum

clocking (SSC), non-spread spectrum clock and two test

modes which are controlled by the SSC_CTL[1:0] pins. Un-

like other synthesizers, the ICS8431-01 can immediately

change spread-spectrum operation without having to reset

the device.

• LVTTL/ LVCMOS control inputs

• PLL bypass modes supporting in-circuit testing and on-chip

functional block characterization

• 28 lead SOIC

In SSC mode, the output clock is modulated in order to

achieve a reduction in EMI. In one of the PLL bypass test

modes, the PLL is disconnected as the source to the

differential output allowing an external source to be

connnected to the TEST_I/O pin. This is useful for in-

circuit testing and allows the differential output to be driven

at a lower frequency throughout the system clock tree. In the

other PLL bypass mode, the oscillator divider is used as the

source to both the M and the Fout divide by 2. This is useful

for characterizing the oscillator and internal dividers.

• RMS cycle-to-cycle jitter of 2ps

• Typical cycle-to-cycle jitter of 18ps

• 0° to 85°C ambiant operating temperature

BLOCK DIAGRAM

PIN ASSIGNMENT

XTAL1

OSC

VDDI

XTAL2

XTAL1

VDDA

VEE

XTAL2

÷ 16

PLL

RESERVED

PHASE

DETECTOR

SSC_CTL0

SSC_CTL1

VEE

TEST_I/O

VDD

VDDO

FOUT

nFOUT

VEE

VCO

÷ 2

FOUT

nFOUT

÷ M

ICS8431-01

28-Lead SOIC

M Package

TEST_I/O

SSC_CTL0

SSC

Top View

Control

SSC_CTL1

Logic

ICS8431CM-01

www.icst.com/products/hiperclocks.html

REV. A JUNE 5, 2001

12 3 4 5 6 7...11

中文翻译

下载PDF

与ICS8431CM-01相关器件

型号	品牌	获取价格	描述	数据表
ICS8431CM-01LFT	IDT	获取价格	Clock Generator, 200MHz, PDSO28, 7.5 X 18.05 MM, 2.25 MM HEIGHT, MS-013, MO-119, SOIC-28
ICS8431CM-01T	ICSI	获取价格	200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
ICS8431CM-11	ICSI	获取价格	255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
ICS8431CM-11	IDT	获取价格	Clock Generator, 255MHz, PDSO28, 7.50 X 18.05, 2.25 MM HEIGHT, SOIC-28
ICS8431CM-11LFT	IDT	获取价格	Clock Generator, 255MHz, PDSO28, 7.50 X 18.05, 2.25 MM HEIGHT, SOIC-28
ICS8431CM-11T	IDT	获取价格	Clock Generator, 255MHz, PDSO28, 7.50 X 18.05, 2.25 MM HEIGHT, SOIC-28
ICS8431CM-11T	ICSI	获取价格	255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
ICS8431DMI-01	IDT	获取价格	Clock Generator, 200MHz, PDSO28, 7.50 X 18.05 X 2.25 MM, MS-013, MO-119, SOIC-28
ICS8431DMI-01LF	IDT	获取价格	Clock Generator, 200MHz, PDSO28, 7.50 X 18.05 X 2.25 MM, MS-013, MO-119, SOIC-28
ICS8431DMI-01LFT	IDT	获取价格	Clock Generator, 200MHz, PDSO28, 7.50 X 18.05 X 2.25 MM, MS-013, MO-119, SOIC-28

与ICS8431CM-01相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

10
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

4
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

26
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

25

产品中心

服务支持

精选活动

关于我们

帮助中心

ICS8431CM-01

ICS8431CM-01 数据手册

与ICS8431CM-01相关器件

与ICS8431CM-01相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ICS8431CM-01

ICS8431CM-01 数据手册

与ICS8431CM-01相关器件

与ICS8431CM-01相关文章

您还可以找

您在本页遇到什么问题？