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ICS8431AMI-21LF PDF预览

ICS8431AMI-21LF

更新时间: 2024-11-03 11:14:39
品牌 Logo 应用领域
矽成 - ICSI 振荡器晶体振荡器
页数 文件大小 规格书
16页 206K
描述
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

ICS8431AMI-21LF 数据手册

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ICS8431I-21  
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-  
TO-3.3V LVPECL FREQUENCY SYNTHESIZER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
Fully integrated PLL  
The ICS8431I-21 is a general purpose clock fre-  
ICS  
HiPerClockS™  
quency synthesizer for IA64/32 application and a  
member of the HiPerClockS™ family of High Per-  
formance Clock Solutions from ICS.The VCO op-  
erates at a frequency range of 250MHz to 700MHz  
Differential 3.3V LVPECL output  
Crystal oscillator interface  
Output frequency range: 62.5MHz to 350MHz  
Crystal input frequency range: 14MHz to 25MHz  
VCO range: 250MHz to 700MHz  
providing an output frequency range of 62.5MHz to 350MHz.  
The output frequency can be programmed using the parallel in-  
terface, M0 through M8 to the configuration logic, and the output  
divider control pin, DIV_SEL. Spread spectrum clocking is pro-  
grammed via the control inputs SSC_CTL0 and SSC_CTL1.  
Programmable PLL loop divider for generating a variety  
of output frequencies  
Programmable features of the ICS8431I-21 support four op-  
erational modes.The four modes are spread spectrum clock-  
ing (SSC), non-spread spectrum clock and two test modes  
which are controlled by the SSC_CTL[1:0] pins. Unlike other  
synthesizers, the ICS8431I-21 can immediately change  
spread-spectrum operation without having to reset the device.  
Spread Spectrum Clocking (SSC) fixed at 1/2% modulation  
for environments requiring ultra low EMI  
PLL bypass modes supporting in-circuit testing and on-chip  
functional block characterization  
Cycle-to-cycle jitter: 30ps (maximum)  
3.3V supply voltage  
In SSC mode, the output clock is modulated in order to achieve  
a reduction in EMI. In one of the PLL bypass test modes, the  
PLL is disconnected as the source to the differential output  
allowing an external source to be connected to the TEST_I/O  
pin. This is useful for in-circuit testing and allows the differen-  
tial output to be driven at a lower frequency throughout the  
system clock tree. In the other PLL bypass mode, the oscilla-  
tor divider is used as the source to both the M and the Fout  
divide by 2.This is useful for characterizing the oscillator and  
internal dividers.  
-40°C to 85°C ambient operating temperature  
Replaces ICS8431I-01  
Available in both, Standard and RoHS/Lead-Free  
compliant packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
M0  
M1  
M2  
M3  
M4  
M5  
M6  
M7  
M8  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
nP_LOAD  
VCC  
XTAL_IN  
XTAL_OUT  
nc  
nc  
VCCA  
VEE  
MR  
DIV_SEL  
VCCO  
FOUT  
nFOUT  
VEE  
XTAL_IN  
OSC  
XTAL_OUT  
÷ 16  
PLL  
9
PHASE  
DETECTOR  
SSC_CTL0  
SSC_CTL1  
VEE  
TEST_I/O  
VCC  
10  
11  
12  
13  
14  
÷2  
VCO  
÷4  
FOUT  
nFOUT  
÷ M  
ICS8431I-21  
28-Lead SOIC  
TEST_I/O  
7.5mm x 18.05mm x 2.25mm package body  
M Package  
TopView  
SSC  
Control  
Logic  
Configuration  
Logic  
M0:M8  
nP_LOAD  
SSC_CTL0  
SSC_CTL1  
DIV_SEL  
8431AMI-21  
www.icst.com/products/hiperclocks.html  
REV.A AUGUST 2, 2005  
1

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