Datasheet > IBM21S851

IBM21S851

更新时间： 2024-10-29 21:10:59

品牌	Logo	应用领域
国际商业机器公司 - IBM		以太网：16GBASE-T 电信电信集成电路
页数	文件大小	规格书
44页	585K
描述
Ethernet Transceiver, PQFP80, 12 X 12 MM, LQFP-80

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IBM21S851 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Contact Manufacturer	零件包装代码：	QFP
包装说明：	12 X 12 MM, LQFP-80	针数：	80
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.89	JESD-30 代码：	S-PQFP-G80
JESD-609代码：	e0	长度：	12 mm
功能数量：	1	端子数量：	80
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	1.7 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ETHERNET TRANSCEIVER
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	12 mm	Base Number Matches：	1

IBM21S851 数据手册

IBM21S850

IBM21S851

IBM 1394 400Mb/s Physical Layer Transceiver (PHY)

Features

• Designed to provisions of the IEEE 1394 Serial

Bus Standard [1]

• 400Mb/s max data rate; interoperable with

100 & 200Mb/s devices

• Available with one or three ports

• Supports major P1394a enhancements

- Multi-speed Concatenation

- Arbitrated Short Reset

• Advanced Power Management:

- Programmable Power Save Mode on uncon-

nected ports

- Sleep Mode to minimize quiescent power

- Utilizes sophisticated clock gating to reduce

power consumption

• Tolerant of extra IDLE indications which circum-

vents Link-PHY “Bus Collision” conditions

• On-device PLL generates the 50MHz SCLK

using an external 25MHz crystal oscillator

• Supports optional 1394-1995 Isolation Barrier

Feature at Link-PHY Interface

- ACK Accelerated Arbitration

- Three TpBias Regulators

- Connection Debounce

• “Missing SID bits” register

• “No reset on unplug” option

• Fully Compliant with OpenHCI requirements

- Programmable Port Disable

- No phy_ID wrap past 63

• Supports optional IBM Dynamic Termination

Isolation Barrier Feature at Link-PHY Interface

• Interoperable with 5V Link Layer Controllers and

5V Transceivers

• Selectable Link-PHY interface timings

• Single 3.3V power supply

• Cable ports exceed 5kV of ESD protection

(Human Body Model)

Overview

The IBM21S850 and IBM21S851 devices (PHYs)

provide transceivers to implement a three or one

port node in a 1394 cable based network. The PHY

is designed to the provisions of the IEEE 1394-1995

specification [1] and includes many of the P1394a

[2] and all OpenHCI enhancements. These

enhancements include Arbitrated Short Reset (for

uninterrupted Isochronous data transport), multi-

speed concatenation, ACK Accelerated Arbitration

(to improve bandwidth utilization), Connection

Debounce Hysteresis (to avoid “Reset Storms”),

three independent TpBias regulators (providing the

ability to disable individual ports), and numerous

other features.

TPA of the PHY at the other end of the cable.

In addition to providing bus transceivers, the PHY

serializes and deserializes data using Data and

Strobe encoding. Data is sent from the Link Layer

Controller on an eight bit wide parallel bus to the

PHY. The two devices are synchronized by a

49.152MHz reference clock provided by the PHY.

The data is then serialized and transmitted to the

cable as Strobe on TPA and Data on TPB. Received

data is resynchronized to the reference clock and

decoded for parallel transmission to the Link Layer

Controller.

PHY devices communicate their speed capabilities

to one another through a process called Speed Sig-

naling, in which common mode currents are with-

drawn from the cable at TPB and TPB. Three such

common mode currents exist for this PHY: one for

each of the supported transfer speeds. The nominal

common mode currents are defined for 100Mb/s,

200Mb/s, and 400Mb/s as 0mA, -3.5mA, and -10mA

respectively. The PHY is capable of 100, 200 or

400Mbits/sec operation, and will send or receive

data at any of these speeds according to the capa-

bilities of the adjacent PHYs.

Each cable port is composed of two differential line

transceivers (TPA and TPB) that transmit and

receive serial data at 100, 200, or 400Mb/s (actually

98.304, 196.608, and 393.216Mb/s, respectively),

depending on which data speed is routed through

the bus. Each transceiver contains a differential cur-

rent mode driver whose outputs provide signal

swings around a common mode voltage called

TpBias, which is generated on the PHY device. Two

off-device 55 ohm resistors are connected in series

across the differential outputs of each transceiver.

TpBias voltage is connected to the midpoint connec-

tion of the resistors at TPA, while a 5K ohm resistor

and a 250pF capacitor to ground are attached to the

midpoint connection of the resistors at TPB. The

TpBias voltage for the TPB line is supplied by the

Other functions of the PHY include system initializa-

tion and bus arbitration. The PHY also determines

whether its ports are connected to other ports by

detecting the presence or absence of TpBias volt-

Use is further subject to the provisions at the end of this document.

phy400.02

11/24/98

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