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IBM25CPC700BB3B83 PDF预览

IBM25CPC700BB3B83

更新时间: 2024-02-03 18:20:52
品牌 Logo 应用领域
国际商业机器公司 - IBM 时钟PC外围集成电路
页数 文件大小 规格书
2页 57K
描述
PCI Bus Controller, CMOS, CBGA474, CERAMIC, BGA-474

IBM25CPC700BB3B83 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:BGA, BGA474,19X25,50针数:474
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.82
Is Samacsys:N地址总线宽度:32
总线兼容性:POWERPC 60X; POWERPC 7XX最大时钟频率:83.33 MHz
外部数据总线宽度:64JESD-30 代码:R-CBGA-B474
长度:32.5 mm端子数量:474
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:BGA
封装等效代码:BGA474,19X25,50封装形状:RECTANGULAR
封装形式:GRID ARRAY电源:3.3 V
认证状态:Not Qualified座面最大高度:3.05 mm
子类别:Other Microprocessor ICs最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM宽度:25 mm
uPs/uCs/外围集成电路类型:BUS CONTROLLER, PCIBase Number Matches:1

IBM25CPC700BB3B83 数据手册

 浏览型号IBM25CPC700BB3B83的Datasheet PDF文件第2页 
CPC700 Memory Controller and PCI Bridge  
High-performancecompanionchipforPowerPC60xand7xxprocessors  
General  
• Provides error tracking/status  
Overview  
• Extensive programmability  
• lwarx/stwx support (reservation cancel-  
ling snoops)  
The CPC700TM Memory Controller and  
PCI Bridge brings high-performance,  
real-time control to PowerPC 60x/7xx  
driven designs. This single-chip micro-  
processor companion is specifically  
designed for embedded systems to  
provide a general purpose bridge to any  
PCI bus.The CPC700 companion chip  
also includes a high-speed memory  
controller, internal peripherals, and  
control for external ROM and external  
peripherals.  
• Flexible and programmable  
error handling  
• Supports Address Only cycle  
ProcessorInterface  
MemoryController  
The PowerPCTM processor bus interface  
includes the interface to the system  
memory controller, as well as the  
Processor Local Bus (PLB) master/slave  
interface.  
This memory controller provides the  
local PowerPC processor with a low-  
latency access path supporting external  
peripherals and 5 banks of local memory.  
SDRAM  
• 1 level processor address pipelining  
• Processor bus arbiter  
• Up to 4 banks  
11x9 to 13x11 addressing (for 2 and 4  
internal bank SDRAMs)  
• L1 cache coherency support  
Two 32-byte write buffers  
This CPC700 companion chip can  
function as a host bridge, as the basis for  
an intelligent add-in PCI controller, or in  
stand-alone modes. This versatility and  
the following features can help lower  
costs, enhance board efficiency and  
reduce your time-to-market.  
• 8 MB to 512 MB per bank  
Data  
Addr.  
32-Bi t  
Control  
ECC  
8-Bi t  
Data  
Addr. Control  
13-Bi t  
64-Bi t  
32 or 64-Bi t  
• PowerPC 60x/7xx interface (66 MHz)  
• 66 MHz SDRAM interface  
UART  
UART  
Memory Controller  
(SDRAM, ROM,  
Peripherals)  
Processor Interface  
64-Bi t  
• External peripheral bus  
32-Bi t  
• PCI 2.1 compliant interface  
(32-bit, 25 to 66 MHz)  
2C  
I
66 MHz Processor Local Bus (PLB)  
• Supports internal or external PCI  
bus arbitration  
32-Bi t  
OPB  
Bridge  
2C  
I
• Interrupt controller  
PCI Interface  
Timers  
Interrupt  
Controller  
• Programmable timers  
Two full-duplex UARTs (16550)  
Two I2C interfaces  
JTAG  
32-Bi t  
Data/Address Control  
• Byte swapping options ease  
communication in little-endian systems  
CPC700BlockDiagram  
• JTAG for board-level testing  

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