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IBM25CPC710CF3A100 PDF预览

IBM25CPC710CF3A100

更新时间: 2024-01-25 22:31:27
品牌 Logo 应用领域
国际商业机器公司 - IBM PC外围集成电路
页数 文件大小 规格书
54页 430K
描述
PCI Bus Controller, CMOS, PBGA728, 35 MM, PLASTIC, FLIP CHIP, BGA-728

IBM25CPC710CF3A100 技术参数

生命周期:Contact Manufacturer零件包装代码:BGA
包装说明:BGA, BGA728,27X27,50针数:728
Reach Compliance Code:unknown风险等级:5.76
地址总线宽度:32外部数据总线宽度:64
JESD-30 代码:S-PBGA-B728长度:35 mm
端子数量:728封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA728,27X27,50
封装形状:SQUARE封装形式:GRID ARRAY
电源:2.5,3.3 V认证状态:Not Qualified
座面最大高度:3.45 mm子类别:Other Microprocessor ICs
最大供电电压:2.56 V最小供电电压:2.44 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
宽度:35 mmuPs/uCs/外围集成电路类型:BUS CONTROLLER, PCI
Base Number Matches:1

IBM25CPC710CF3A100 数据手册

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Preliminary  
CPC710 PCI Bridge and Memory Controller Data Sheet  
Features  
• IBM CPC710 PowerPCto PCI bridge  
- Two-way interleaved operation with ECC  
using external multiplexer  
- 2.5V PPC60x processor bus running at up  
to 133MHz  
- Up to 3.5GB addressing space using 16-,  
64-,128-, 256-, 512- or 1024-MB DIMMs  
- Dual 32- and 64-bit PCI interfaces  
- 100- and 133-MHz SDRAM interface  
- Internal DMA controller  
• PPC60x Bus interface  
- Up to 133MHz bus  
- One to four processors  
- 2-MB Flash boot ROM support  
- 256-MB Extended Flash support  
- JTAG for board level testing  
- Up to 6 outstanding transaction requests  
- Little Endian mode available  
• System I/O interface  
- 2-MB Flash Boot ROM  
- 256-MB Extended Flash  
• PCI interfaces  
- Two independent bridges with parking  
- PCI Revision 2.1 compliant  
- 3.3V signal interface  
• DMA controller  
- Single channel  
• Synchronous DRAM (SDRAM) interface  
operating at 100 or 133MHz  
- System memory-to-PCI transfers only  
- Store-gather for enhanced performance  
- Support for PC100 and PC133 SDRAM and  
Registered DIMMs  
Description  
The CPC710 IBM PCI Bridge and Memory  
Controller is a highly integrated host bridge device  
that interfaces PowerPC 60x buses to SDRAM-  
based system memory and also provides two PCI  
interfaces. It supports up to four processors with  
pipelining for up to six outstanding transaction  
requests.  
supports a standard 32-bit, 33MHz PCI bus, while  
the other supports 64 bits at up to 66MHz for  
graphics and high speed communications.  
An internal DMA controller allows high speed data  
transfer between Memory and I/O. Store-gathering  
enhances the CPU-to-I/O performance.  
The memory controller supports SDRAM, allowing  
the memory to burst data on most bus cycles at  
100MHz or 133MHz.  
Technology: IBM CMOS SA-12E, 0.25 µm  
Package: 35mm, 728-ball flip chip-plastic ball grid  
array (FC-PBGA)  
For system designs requiring high I/O bandwidth,  
there are two PCI host bus bridges. One bridge  
Power (estimated): Typical 2.1W, Maximum 2.6W  
While the information contained herein is believed to be accurate, such information is preliminary, and should not be  
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.  
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