Datasheet > IBM041811QLAB-6

IBM041811QLAB-6

更新时间： 2024-11-03 07:13:31

品牌	Logo	应用领域
国际商业机器公司 - IBM		静态存储器
页数	文件大小	规格书
21页	301K
描述
Standard SRAM, 64KX18, 3ns, CMOS, PBGA119, BGA-119

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IBM041811QLAB-6 数据手册

IBM043611QLAB

IBM041811QLAB

Preliminary

Features

32K X 36 & 64K X 18 SRAM

• Common I/O

• 32K x 36 or 64K x 18 Organizations

• 0.5 Micron CMOS Technology

• Asynchronous Output Enable and Power Down

Inputs

• Synchronous Pipeline Mode Of Operation with

Self-Timed Late Write

• Boundary Scan using limited set of JTAG 1149.1

functions

• Single Differential GTL/HSTL Clock

• Single +3.3V Power Supply and Ground

• GTL/HSTL Input and Output levels

• Byte Write Capability & Global Write Enable

• 7 X 17 Bump Ball Grid Array Package with

SRAM JEDEC Standard Pinout and Boundary

SCAN Order

• Registered Addresses, Write Enables, Synchro-

nous Select and Data Ins.

• Programmable Impedance Output Drivers

• Registered Outputs

Description

The IBM043611QLA and IBM041811QLA 1Mb

SRAMS are Synchronous Pipeline Mode, high per-

formance CMOS Static Random Access Memories

that are versatile, wide I/O, and achieves 5 nsec

cycle times. Differential K clocks are used to initiate

the read/write operation and all internal operations

are self-timed. At the rising edge of the K Clock, all

Addresses, Write-Enables, Sync Select and Data

Ins are registered internally. Data Outs are updated

from output registers off the next rising edge of the K

clock. An internal Write buffer allows write data to

follow one cycle after addresses and controls. The

chip is operated with a single +3.3V power supply

and is compatible with GTL/HSTL I/O interfaces.

Use is further subject to the provisions at the end of this document.

03H9040

SA14-4659-04

Revised 7/96

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IBM041811TLAB-6	IBM	获取价格	Standard SRAM, 64KX18, 3ns, CMOS, PBGA119, BGA-119