Datasheet > IBM041811TLAB-5

IBM041811TLAB-5

更新时间： 2024-09-29 08:21:39

品牌	Logo	应用领域
国际商业机器公司 - IBM		静态存储器
页数	文件大小	规格书
22页	319K
描述
Standard SRAM, 64KX18, 2.5ns, CMOS, PBGA119, BGA-119

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IBM041811TLAB-5 数据手册

IBM043611TLAB4M

x 1612/10, 3.3VMMDM15DSU-021045122.

IBM041811TLAB

IBM043611TLAB

Preliminary

Features

32K x 36 & 64K x 18 SRAM

• 32K x 36 or 64K x 18 Organizations

• 0.45 Micron CMOS Technology

• Common I/O

• Asynchronous Output Enable and Power Down

Inputs

• Synchronous Pipeline Mode of Operation with

Self-Timed Late Write

• Boundary Scan using limited set of JTAG 1149.1

functions

• Single Differential HSTL/GTL Clock

• Single +3.3V Power Supply and Ground

• HSTL/GTL Input and Output levels

• Byte Write Capability & Global Write Enable

• 7 x 17 Bump Ball Grid Array Package with

SRAM EDEC Standard Pinout and Boundary

SCAN Order

• Registered Addresses, Write Enables, Synchro-

nous Select, and Data Ins

• Programmable Impedance Output Drivers

• Registered Outputs

Description

The IBM043611TLAB and IBM041811TLAB 1Mb

SRAMS are Synchronous Pipeline Mode, high-per-

formance CMOS Static Random Access Memories

that are versatile, have wide I/O, and achieve 4ns

cycle times. Dual differential K clocks are used to ini-

tiate the read/write operation, and all internal opera-

tions are self-timed. At the rising edge of the K clock,

all Addresses, Write-Enables, Sync Select, and

Data Ins are registered internally. Data Outs are

updated from output registers off the next rising

edge of the K clock. An internal Write buffer allows

write data to follow one cycle after addresses and

controls. The chip is operated with a single +3.3V

power supply and is compatible with HSTL/GTL I/O

interfaces.

Use is further subject to the provisions at the end of this document.

77H9965.T5

10/98

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