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HY5Y5A6DF-PF PDF预览

HY5Y5A6DF-PF

更新时间: 2024-02-19 17:02:59
品牌 Logo 应用领域
海力士 - HYNIX 时钟动态存储器内存集成电路
页数 文件大小 规格书
23页 386K
描述
Synchronous DRAM, 16MX16, 7ns, CMOS, PBGA54

HY5Y5A6DF-PF 技术参数

生命周期:Obsolete包装说明:FBGA, BGA54,9X9,32
Reach Compliance Code:compliant风险等级:5.84
最长访问时间:7 ns最大时钟频率 (fCLK):105 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:S-PBGA-B54内存密度:268435456 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
端子数量:54字数:16777216 words
字数代码:16000000最高工作温度:70 °C
最低工作温度:-25 °C组织:16MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:FBGA封装等效代码:BGA54,9X9,32
封装形状:SQUARE封装形式:GRID ARRAY, FINE PITCH
电源:3/3.3 V认证状态:Not Qualified
刷新周期:8192连续突发长度:1,2,4,8,FP
最大待机电流:0.00035 A子类别:DRAMs
最大压摆率:0.165 mA表面贴装:YES
技术:CMOS温度等级:OTHER
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOMBase Number Matches:1

HY5Y5A6DF-PF 数据手册

 浏览型号HY5Y5A6DF-PF的Datasheet PDF文件第6页浏览型号HY5Y5A6DF-PF的Datasheet PDF文件第7页浏览型号HY5Y5A6DF-PF的Datasheet PDF文件第8页浏览型号HY5Y5A6DF-PF的Datasheet PDF文件第10页浏览型号HY5Y5A6DF-PF的Datasheet PDF文件第11页浏览型号HY5Y5A6DF-PF的Datasheet PDF文件第12页 
HY5Y5A6DF-xF  
COMMAND TRUTH TABLE  
A10/  
AP  
Function  
CKEn-1  
CKEn  
CS  
RAS CAS WE DQM ADDR  
BA Note  
Mode Register Set  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
Op Code  
2
2
Extended Mode Register Set  
L
L
L
Op Code  
No Operation  
H
X
L
H
X
H
L
H
X
H
H
H
L
X
X
Device Deselect  
Bank Active  
Read  
Row Address  
V
V
V
V
V
X
V
Column  
L
H
H
H
H
L
Read with Autoprecharge  
Write  
L
X
X
X
X
X
X
X
V
X
X
X
Column  
Column  
Column  
X
H
L
L
Write with Autoprecharge  
L
L
H
H
L
Precharge All Banks  
H
H
H
L
Precharge selected Bank  
L
L
X
Burst stop  
H
L
X
X
X
X
X
X
Data Write/Output Enable  
Data Mask/Output Disable  
Auto Refresh  
X
X
L
L
L
H
H
X
H
X
H
X
H
X
V
Self Refresh Entry  
Self Refresh Exit  
L
L
L
H
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
1
Precharge Power Down  
Entry  
H
L
L
H
L
X
X
X
X
X
X
Precharge Power Down Exit  
Clock Suspend Entry  
Clock Suspend Exit  
H
L
H
L
H
H
L
L
H
L
H
L
X
X
X
X
X
X
X
X
Deep Power Down Entry  
Deep Power Down Exit  
L
H
H
L
H
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.  
2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set.  
Rev. 0.2 / June. 2003  
9

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