Datasheet > HY5Y5A6DFP-HF

HY5Y5A6DFP-HF

更新时间： 2024-01-21 14:32:19

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
25页	220K
描述
DRAM

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技术参数
数据手册

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HY5Y5A6DFP-HF 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

HY5Y5A6DFP-HF 数据手册

Preliminary

HY5Y5A6D(L/S)F(P)-xF

4Banks x 4M x 16bits Synchronous DRAM

DESCRIPTION

The Hynix Low Power SDRAM is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular

phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.

The Hynix HY5Y5A6D(L/S)F(P) is a 268,435,456bit CMOS Synchronous Dynamic Random Access Memory. It is organ-

ized as 4banks of 4,194,304x16.

The Low Power SDRAM provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst

length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Low Power SDRAM

also provides for special programmable options including Partial Array Self Refresh of a quarter bank, a half bank,

1bank, 2banks, or all banks, Temperature Compensated Self Refresh of 15, 45, 70, or 85 degrees ^oC. A burst of Read

or Write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a

new burst Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule).

Deep Power Down Mode is a additional operating mode for Low Power SDRAM. This mode can achieve maximum power

reduction by removing power to the memory array within each SDRAM. By using this feature, the system can cut off

alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout

flexibility.

FEATURES

Standard SDRAM Protocol

Internal 4bank operation

●

Power Supply Voltage : VDD = 3.0V, VDDQ = 3.0V

LVCMOS compatible I/O Interface

Low Voltage interface to reduce I/O power

Low Power Features

- PASR(Partial Array Self Refresh)

- TCSR (Temperature Compensated Self Refresh)

- DS (Drive Strength)

- Deep Power Down Mode

●

Programmable CAS latency of 1, 2 or 3

-25^oC ~ 70^oC Operation

Package Type : 54ball, 0.8mm pitch FBGA (Lead Free, Lead)

HY5Y5A6D(L/S)FP : Lead Free

HY5Y5A6D(L/S)F : Lead

256M SDRAM ORDERING INFORMATION

CAS

Latency

Part Number

Clock Frequency

Organization

Interface 54Ball FBGA

HY5Y5A6D(L/S)F-HF

HY5Y5A6D(L/S)FP-HF

Lead

LVCMOS

133MHz

4banks x 4Mb x 16

Lead Free

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 0.3 / Aug. 2003

12 3 4 5 6 7...25

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与HY5Y5A6DFP-HF相关器件

型号	品牌	描述	获取价格	数据表
HY5Y5A6DF-SF	HYNIX	Synchronous DRAM, 16MX16, 7ns, CMOS, PBGA54	获取价格
HY5Y5A6DLF-HF	HYNIX	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 0.80 MM PITCH, FBGA-54	获取价格
HY5Y5A6DLF-PF	HYNIX	Synchronous DRAM, 16MX16, 7ns, CMOS, PBGA54	获取价格
HY5Y5A6DLFP-HF	HYNIX	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 0.80 MM PITCH, LEAD FREE, FBGA-54	获取价格
HY5Y5A6DLF-SF	HYNIX	Synchronous DRAM, 16MX16, 7ns, CMOS, PBGA54	获取价格
HY5Y5A6DSF-HF	HYNIX	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 0.80 MM PITCH, FBGA-54	获取价格