Datasheet > HY5Y5A6DSFP-HF

HY5Y5A6DSFP-HF

更新时间： 2024-01-29 05:29:16

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器内存集成电路
页数	文件大小	规格书
25页	1637K
描述
Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 0.80 MM PITCH, LEAD FREE, FBGA-54

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HY5Y5A6DSFP-HF 技术参数

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	TFBGA,	针数：	54
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.24	风险等级：	5.84
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	5.4 ns
其他特性：	AUTO/SELF REFRESH	JESD-30 代码：	R-PBGA-B54
JESD-609代码：	e1	长度：	13.5 mm
内存密度：	268435456 bit	内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	16	功能数量：	1
端口数量：	1	端子数量：	54
字数：	16777216 words	字数代码：	16000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：	-25 °C	组织：	16MX16
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH
认证状态：	Not Qualified	座面最大高度：	1.1 mm
自我刷新：	YES	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2.7 V	标称供电电压 (Vsup)：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子面层：	TIN SILVER COPPER
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	宽度：	8 mm
Base Number Matches：	1

HY5Y5A6DSFP-HF 数据手册

Preliminary

HY5Y5A6D(L/S)F(P)-xF

4Banks x 4M x 16bits Synchronous DRAM

DESCRIPTION

The Hynix Mobile SDR is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular

phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.

The Hynix HY5Y5A6D(L/S)F(P) is a 268,435,456bit CMOS Synchronous Dynamic Random Access Memory. It is organ-

ized as 4banks of 4,194,304x16.

The Mobile SDR provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst length of

1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Mobile SDR also provides for

special programmable options including Partial Array Self Refresh of a quarter bank, a half bank, 1bank, 2banks, or all

banks, Temperature Compensated Self Refresh of 15, 45, 70, or 85 degrees C. A burst of Read or Write cycles in

progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or

Write command on any cycle(This pipelined design is not restricted by a 2N rule).

Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power re-

duction by removing power to the memory array within each SDR. By using this feature, the system can cut off alomost

all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout flexibility.

FEATURES

Standard SDR Protocol

Internal 4bank operation

●

Power Supply Voltage : VDD = 3.0V, VDDQ = 3.0V

LVCMOS compatible I/O Interface

Low Voltage interface to reduce I/O power

Low Power Features

- PASR(Partial Array Self Refresh)

- TCSR (Temperature Compensated Self Refresh)

- DS (Drive Strength)

- Deep Power Down Mode

●

Programmable CAS latency of 1, 2 or 3

-25^oC ~ 70^oC Operation

Package Type : 54ball, 0.8mm pitch FBGA (Lead Free, Lead)

HY5Y5A6D(L/S)FP : Lead Free

HY5Y5A6D(L/S)F : Lead

ORDERING INFORMATION

CAS

Latency

Part Number

Clock Frequency

Organization

Interface 54Ball FBGA

HY5Y5A6D(L/S)F-HF

HY5Y5A6D(L/S)FP-HF

Lead

LVCMOS

133MHz

4banks x 4Mb x 16

Lead Free

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 0.3 / Aug. 2003

12 3 4 5 6 7...25

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与HY5Y5A6DSFP-HF相关器件

型号	品牌	描述	获取价格	数据表
HY5Y5A6DSF-SF	HYNIX	Synchronous DRAM, 16MX16, 7ns, CMOS, PBGA54	获取价格
HY5Y6B6DLF-HF	HYNIX	4Banks x1M x 16bits Synchronous DRAM	获取价格
HY5Y6B6DLF-PF	HYNIX	4Banks x1M x 16bits Synchronous DRAM	获取价格
HY5Y6B6DLFP-HF	HYNIX	4Banks x1M x 16bits Synchronous DRAM	获取价格
HY5Y6B6DLFP-PF	HYNIX	4Banks x1M x 16bits Synchronous DRAM	获取价格
HY5Y7A2DLM-HF	HYNIX	4Banks x 4M x 32bits Synchronous DRAM	获取价格

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