Datasheet > HY5Y5A6DSFP-HF

HY5Y5A6DSFP-HF

更新时间： 2024-01-26 15:00:11

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器内存集成电路
页数	文件大小	规格书
25页	1637K
描述
Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 0.80 MM PITCH, LEAD FREE, FBGA-54

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

HY5Y5A6DSFP-HF 技术参数

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	TFBGA,	针数：	54
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.24	风险等级：	5.84
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	5.4 ns
其他特性：	AUTO/SELF REFRESH	JESD-30 代码：	R-PBGA-B54
JESD-609代码：	e1	长度：	13.5 mm
内存密度：	268435456 bit	内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	16	功能数量：	1
端口数量：	1	端子数量：	54
字数：	16777216 words	字数代码：	16000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：	-25 °C	组织：	16MX16
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH
认证状态：	Not Qualified	座面最大高度：	1.1 mm
自我刷新：	YES	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2.7 V	标称供电电压 (Vsup)：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子面层：	TIN SILVER COPPER
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	宽度：	8 mm
Base Number Matches：	1

HY5Y5A6DSFP-HF 数据手册

Preliminary

HY5Y5A6D(L/S)F(P)-xF

4Banks x 4M x 16bits Synchronous DRAM

Power Up and Initialization

Like a Synchronous DRAM, Mobile SDR must be powered up and initialized in a predefined manner. Power must be

applied to VDD and VDDQ(simultaneously). The clock signal must be started at the same time. After power up, an initial

pause of 200 usec is required. And a precharge all command will be issued to the Mobile SDR. Then, 8 or more Auto

refresh cycles will be provided. After the Auto refresh cycles are completed, a mode register set(MRS) command will

be issued to program the specific mode of operation (Cas Latency, Burst length, etc.) And a extended mode register

set command will be issued to program specific mode of self refresh operation(PASR, TCSR). The following these cycles,

the Mobile SDR is ready for normal opeartion.

Programming the registers

Mode Register

The mode register contains the specific mode of operation of the Mobile SDR. This register includes the selection of a

burst length(1, 2, 4, 8, Full Page), a cas latency(1, 2 or 3), a burst type. The mode register set must be done before

any activate command after the power up sequence. Any contents of the mode register be altered by re-programming

the mode register through the execution of mode register set command.

Extended Mode Register

The extended mode register contains the specific features of self refresh opeartion and drive strength of the Mobile

SDR. This register includes the selection of partial arrays to be refreshed(half array, quarter array, etc.), tempearture

range of the device(85^oC, 70^oC, 45^oC, 15^oC) for reducing current consumption during self refresh and drive strength

(full, 1/2 strength, 1/4 strength).

The extended mode register set must be done before any activate command after the power up sequence. Any contents

of the extended mode register be altered by re-programming the extended mode register through the execution of ex-

tended mode register set command.

Bank(Row) Active

The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by

activating CS, RAS and deasserting CAS, WE at the positive edge of the clock. The value on the BA1 and BA0 selects

the bank, and the value on the A0-A12 selects the row. This row remains active for column access until a precharge

command is issued to that bank. Read and write operations can only be initiated on this activated bank after the min-

imum tRCD time is passed from the activate command.

Read

The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and

deasserting WE, RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select

the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Pre-

charge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not

selected, the row will remain active for subsequent accesses.

The length of burst and the CAS latency will be determined by the values programmed during the MRS command.

Write

The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE

and deasserting RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select

the starting column location. The value on input A10 determines whether or not Auto Precharge is used.

If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Pre-

charge is not selected, the row will remain active for subsequent accesses.

Rev 0.3 / Aug. 2003

1...4 5 678 9 10...25

下载PDF

与HY5Y5A6DSFP-HF相关器件

型号	品牌	描述	获取价格	数据表
HY5Y5A6DSF-SF	HYNIX	Synchronous DRAM, 16MX16, 7ns, CMOS, PBGA54	获取价格
HY5Y6B6DLF-HF	HYNIX	4Banks x1M x 16bits Synchronous DRAM	获取价格
HY5Y6B6DLF-PF	HYNIX	4Banks x1M x 16bits Synchronous DRAM	获取价格
HY5Y6B6DLFP-HF	HYNIX	4Banks x1M x 16bits Synchronous DRAM	获取价格
HY5Y6B6DLFP-PF	HYNIX	4Banks x1M x 16bits Synchronous DRAM	获取价格
HY5Y7A2DLM-HF	HYNIX	4Banks x 4M x 32bits Synchronous DRAM	获取价格

与HY5Y5A6DSFP-HF相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

15
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

15
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

12
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

10

产品中心

服务支持

精选活动

关于我们

帮助中心

HY5Y5A6DSFP-HF

HY5Y5A6DSFP-HF 技术参数

HY5Y5A6DSFP-HF 数据手册

与HY5Y5A6DSFP-HF相关器件

与HY5Y5A6DSFP-HF相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

HY5Y5A6DSFP-HF

HY5Y5A6DSFP-HF 技术参数

HY5Y5A6DSFP-HF 数据手册

与HY5Y5A6DSFP-HF相关器件

与HY5Y5A6DSFP-HF相关文章

您还可以找

您在本页遇到什么问题？