Datasheet > HY5Y5A6DF-PF

HY5Y5A6DF-PF

更新时间： 2024-01-15 04:09:18

品牌	Logo	应用领域
海力士 - HYNIX		时钟动态存储器内存集成电路
页数	文件大小	规格书
23页	386K
描述
Synchronous DRAM, 16MX16, 7ns, CMOS, PBGA54

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技术参数
数据手册

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HY5Y5A6DF-PF 技术参数

生命周期：	Obsolete	包装说明：	FBGA, BGA54,9X9,32
Reach Compliance Code：	compliant	风险等级：	5.84
最长访问时间：	7 ns	最大时钟频率 (fCLK)：	105 MHz
I/O 类型：	COMMON	交错的突发长度：	1,2,4,8
JESD-30 代码：	S-PBGA-B54	内存密度：	268435456 bit
内存集成电路类型：	SYNCHRONOUS DRAM	内存宽度：	16
端子数量：	54	字数：	16777216 words
字数代码：	16000000	最高工作温度：	70 °C
最低工作温度：	-25 °C	组织：	16MX16
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	FBGA	封装等效代码：	BGA54,9X9,32
封装形状：	SQUARE	封装形式：	GRID ARRAY, FINE PITCH
电源：	3/3.3 V	认证状态：	Not Qualified
刷新周期：	8192	连续突发长度：	1,2,4,8,FP
最大待机电流：	0.00035 A	子类别：	DRAMs
最大压摆率：	0.165 mA	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	Base Number Matches：	1

HY5Y5A6DF-PF 数据手册

HY5Y5A6DF-xF

Power Up and Initialization

Like a Synchronous DRAM, Low Power SDRAM must be powered up and initialized in a predefined manner. Power must

be applied to VDD and VDDQ(simultaneously). The clock signal must be started at the same time. After power up, an initial

pause of 200 µsec is required. And a precharge all command will be issued to the LP SDRAM. Then, 8 or more Auto refresh

cycles will be provided. After the Auto refresh cycles are completed, a mode register set(MRS) command will be issued to

program the specific mode of operation (Cas Latency, Burst length, etc.) And a extended mode register set command will

be issued to program specific mode of self refresh operation(PASR & TCSR). Following these cycles, the LP SDRAM is

ready for normal opeartion.

Programming the registers

Mode Register

The mode register contains the specific mode of operation of the LP SDRAM. This register includes the selection of a burst

length(1, 2, 4, 8, Full Page), a cas latency(1, 2, or 3), a burst type, an opearting mode to differentiate between normal mode

and a special burst read and single write mode. The mode register set must be done before any activate command after the

power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execu-

tion of mode register set command.

Extended Mode Register

The extended mode register contains the specific features of self refresh opeartion and drive strength of the LP SDRAM.

This register includes the selection of partial arrays to be refreshed(half array, quarter array, etc.), tempearture range of the

device(85, 70, 45, 15) for reducing current consumption during self refresh and drive strength (full, 1/2 strength, 1/4 strength).

The extended mode register set must be done before any activate command after the power up sequence. Any contents of

the extended mode register be altered by re-programming the extended mode register through the execution of extended

mode register set command.

Bank(Row) Active

The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating

CS, RAS and deasserting CAS, WE at the positive edge of the clock. The value on the BA1 and BA0 selects the bank, and

the value on the A0-A12 selects the row. This row remains active for column access until a precharge command is issued

to that bank. Read and write opeartions can only be initiated on this activated bank after the minimum tRCD time is passed

from the activate command.

Read

The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and deas-

serting WE, RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the

starting column location. The value on input A10 determines whether Auto Precharge is used or not. If Auto Precharge is

selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not selected, the row

will remain active for subsequent accesses.The length of burst and the CAS latency will be determined by the values pro-

grammed during the MRS command.

Write

The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE and

deasserting RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the

starting column location. The value on input A10 determines whether Auto Precharge is used or not. If Auto Precharge is

selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Precharge is not selected, the

row will remain active for subsequent accesses.

Rev. 0.2 / June. 2003

1...4 5 678 9 10...23

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与HY5Y5A6DF-PF相关器件

型号	品牌	描述	获取价格	数据表
HY5Y5A6DFP-HF	HYNIX	DRAM	获取价格
HY5Y5A6DF-SF	HYNIX	Synchronous DRAM, 16MX16, 7ns, CMOS, PBGA54	获取价格
HY5Y5A6DLF-HF	HYNIX	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 0.80 MM PITCH, FBGA-54	获取价格
HY5Y5A6DLF-PF	HYNIX	Synchronous DRAM, 16MX16, 7ns, CMOS, PBGA54	获取价格
HY5Y5A6DLFP-HF	HYNIX	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 0.80 MM PITCH, LEAD FREE, FBGA-54	获取价格
HY5Y5A6DLF-SF	HYNIX	Synchronous DRAM, 16MX16, 7ns, CMOS, PBGA54	获取价格

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