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HY5W2A2SF-P

更新时间： 2024-11-09 19:51:59
品牌 Logo 应用领域
海力士 - HYNIX 时钟动态存储器内存集成电路
页数 文件大小 规格书
25页 399K
描述
Synchronous DRAM, 4MX32, 7ns, CMOS, PBGA90, 0.80 MM PITCH, FBGA-90

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HY5W2A2SF-P 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：TFBGA, BGA90,9X15,32针数：90
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.02风险等级：5.84
访问模式：FOUR BANK PAGE BURST最长访问时间：7 ns
其他特性：AUTO/SELF REFRESH最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMON交错的突发长度：1,2,4,8
JESD-30 代码：R-PBGA-B90JESD-609代码：e1
长度：13 mm内存密度：134217728 bit
内存集成电路类型：SYNCHRONOUS DRAM内存宽度：32
功能数量：1端口数量：1
端子数量：90字数：4194304 words
字数代码：4000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-25 °C
组织：4MX32输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装等效代码：BGA90,9X15,32封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：1.8/2.5,2.5 V认证状态：Not Qualified
刷新周期：4096座面最大高度：1.2 mm
自我刷新：YES连续突发长度：1,2,4,8,FP
最大待机电流：0.0006 A子类别：DRAMs
最大压摆率：0.13 mA最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：8 mmBase Number Matches：1

HY5W2A2SF-P 数据手册

 浏览型号HY5W2A2SF-P的Datasheet PDF文件第2页浏览型号HY5W2A2SF-P的Datasheet PDF文件第3页浏览型号HY5W2A2SF-P的Datasheet PDF文件第4页浏览型号HY5W2A2SF-P的Datasheet PDF文件第5页浏览型号HY5W2A2SF-P的Datasheet PDF文件第6页浏览型号HY5W2A2SF-P的Datasheet PDF文件第7页 
HY5W2A2(L/S)F / HY57W2A3220(L/S)T  
HY5W22F / HY57W283220T  
4Banks x 1M x 32bits Synchronous DRAM  
DESCRIPTION  
The Hynix Low Power SDRAM is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G  
cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs  
The Hynix HY5W2A2F series is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory applica-  
tions which require wide data I/O and high bandwidth. HY5W2A2F series is organized as 4banks of 1,048,576x32.  
The Low Power SDRAM provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst  
length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Low Power SDRAM  
also provides for special programmable options including Partial Array Self Refresh of 1bank, 2banks, or all banks,  
Temperature Compensated Self Refresh of 15, 45, 70, or 85 degrees C. A burst of Read or Write cycles in progress  
can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or Write  
command on any cycle(This pipelined design is not restricted by a 2N rule).  
Deep Power Down Mode is a additional operating mode for Low Power SDRAM. This mode can achieve maximum  
power reduction by removing power to the memory array within each SDRAM. By using this feature, the system can  
cut off alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-line lay-  
out flexibility.  
FEATURES  
•
•
•
•
•
•
Standard SDRAM Protocol  
Internal 4bank operation  
Voltage : VDD = 2.5V, VDDQ = 1.8V & 2.5V  
LVTTL compatible I/O Interface  
Low Voltage interface to reduce I/O power  
Low Power Features ( HY5W22F / HY57W283220T series can’t support these features)  
- PASR(Partial Array Self Refresh)  
- TCSR(Temperature Compensated Self Refresh)  
- Deep Power Down Mode  
Packages : 90ball, 0.8mm pitch FBGA / 86pin, TSOP  
-25 ~ 85C Operation  
•
•
ORDERING INFORMATION  
Clock Frequency  
Part No.  
Organization  
Interface  
Package  
CAS Latench  
HY57W2A3220(L/S)T-H  
HY5W2A2(L/S)F-H  
133MHz  
CL 3  
4Banks x 1Mbits  
x32  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
HY57W2A3220(L/S)T-8  
HY5W2A2(L/S)F-8  
125MHz  
CL 3  
4Banks x 1Mbits  
x32  
90balls FBGA  
(HY5xxxxxxF)  
86pin TSOP-II  
(HY5xxxxxxT)  
HY57W2A3220(L/S)T-P  
HY5W2A2(L/S)F-P  
100MHz  
CL 2  
4Banks x 1Mbits  
x32  
HY57W2A3220(L/S)T-S  
HY5W2A2(L/S)F-S  
100MHz  
CL 3  
4Banks x 1Mbits  
x32  
HY57W2A3220(L/S)T-B  
HY5W2A2(L/S)F-B  
66MHz  
CL 2  
4Banks x 1Mbits  
x32  
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume  
any responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.5/Jan. 03  
1234567...25

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与HY5W2A2SF-P相关器件

型号 品牌 获取价格 描述 数据表
HY5W2A6CF-H HYNIX

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 		Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54
HY5W2A6CF-P HYNIX

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 		Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54
HY5W2A6CF-PF HYNIX

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 		Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54
HY5W2A6CF-S HYNIX

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 		Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54
HY5W2A6CLF-B HYNIX

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 		Synchronous DRAM, 8MX16, 9ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54
HY5W2A6CLF-H ETC

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 		x16 SDRAM
HY5W2A6CLF-HF HYNIX

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 		Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54
HY5W2A6CLF-P HYNIX

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 		Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54
HY5W2A6CLF-PF HYNIX

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 		Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54
HY5W2A6CLF-S HYNIX

获取价格

 		Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54

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