Datasheet > HY5W2A6CF-S

HY5W2A6CF-S

更新时间： 2024-01-14 21:53:24

品牌	Logo	应用领域
海力士 - HYNIX		时钟动态存储器内存集成电路
页数	文件大小	规格书
24页	407K
描述
Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54

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技术参数
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HY5W2A6CF-S 技术参数

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	TFBGA, BGA54,9X9,32	针数：	54
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.02	风险等级：	5.84
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	7 ns
其他特性：	AUTO/SELF REFRESH	最大时钟频率 (fCLK)：	100 MHz
I/O 类型：	COMMON	交错的突发长度：	1,2,4,8
JESD-30 代码：	R-PBGA-B54	JESD-609代码：	e1
长度：	10.5 mm	内存密度：	134217728 bit
内存集成电路类型：	SYNCHRONOUS DRAM	内存宽度：	16
功能数量：	1	端口数量：	1
端子数量：	54	字数：	8388608 words
字数代码：	8000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-25 °C
组织：	8MX16	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFBGA
封装等效代码：	BGA54,9X9,32	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH	电源：	1.8/2.5,2.5 V
认证状态：	Not Qualified	刷新周期：	4096
座面最大高度：	1.07 mm	自我刷新：	YES
连续突发长度：	1,2,4,8,FP	最大待机电流：	0.0005 A
子类别：	DRAMs	最大压摆率：	0.125 mA
最大供电电压 (Vsup)：	2.7 V	最小供电电压 (Vsup)：	2.3 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	TIN SILVER COPPER	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
宽度：	8.3 mm	Base Number Matches：	1

HY5W2A6CF-S 数据手册

HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T

HY5W26CF / HY57W281620HCT

4Banks x 2M x 16bits Synchronous DRAM

DESCRIPTION

The Hynix Low Power SDRAM is suited for non-PC application which use the batteries such as PDAs,

2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld

PCs.

The Hynix HY5W2A6CF is a 134,217,728bit CMOS Synchronous Dynamic Random Access Memory. It

is organized as 4banks of 2,097,152x16.

The Low Power SDRAM provides for programmable options including CAS latency of 1, 2, or 3, READ

or WRITE burst length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave).

And the Low Power SDRAM also provides for special programmable options including Partial Array Self

Refresh of a quarter bank, a half bank, 1bank, 2banks, or all banks, Temperature Compensated Self

Refresh of 15, 45, 70, or 85 degrees C. A burst of Read or Write cycles in progress can be terminated

by a burst terminate command or can be interrupted and replaced by a new burst Read or Write com-

mand on any cycle(This pipelined design is not restricted by a 2N rule).

Deep Power Down Mode is a additional operating mode for Low Power SDRAM. This mode can achieve

maximum power reduction by removing power to the memory array within each SDRAM. By using this

feature, the system can cut off alomost all DRAM power without adding the cost of a power switch and

giving up mother-board power-line layout flexibility.

FEATURES

•

Standard SDRAM Protocol

Internal 4bank operation

Voltage : VDD = 2.5V, VDDQ = 1.8V & 2.5V

LVTTL compatible I/O Interface

Low Voltage interface to reduce I/O power

Low Power Features ( HY5W26CF / HY57W281620HCT series can’t support these features)

- PASR(Partial Array Self Refresh)

- TCSR(Temperature Compensated Self Refresh)

- Deep Power Down Mode

•

CAS latency of 1, 2, or 3

Packages : 54ball, 0.8mm pitch FBGA / 54pin, TSOP

-25 ~ 85C Operation

128M SDRAM ODERING INFORMATION

Clock

CAS

Part Number

Organization

Interface

Package

Frequency Latency

HY5W2A6C(L/S)F-H

HY5W26CF-H

133MHz

100MHz

66Mhz

4banks x 2Mb x 16

LVTTL

HY57W2A1620HC(L/S)T-H

HY57W281620HCT-H

HY5W2A6C(L/S)F-P

HY5W26CF-P

HY57W2A1620HC(L/S)T-P

HY57W281620HCT-P

4banks x 2Mb x 16

LVTTL

54ball FBGA

(HY5xxxxxxF)

54pin TSOP-II

(HY5xxxxxxT)

HY5W2A6C(L/S)F-S

HY5W26CF-S

HY57W2A1620HC(L/S)T-S

HY57W281620HCT-S

HHY5W2A6C(L/S)F-B

HY5W26CF-B

HY57W2A1620HC(L/S)T-B

HY57W281620HCT-B

* HY5xxxxxx-B Series can support 40Mhz CL1 and 33Mhz CL1.

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 1.3 / Dec. 01

12 3 4 5 6 7...24

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与HY5W2A6CF-S相关器件

型号	品牌	描述	获取价格	数据表
HY5W2A6CLF-B	HYNIX	Synchronous DRAM, 8MX16, 9ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54	获取价格
HY5W2A6CLF-H	ETC	x16 SDRAM	获取价格
HY5W2A6CLF-HF	HYNIX	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54	获取价格
HY5W2A6CLF-P	HYNIX	Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54	获取价格
HY5W2A6CLF-PF	HYNIX	Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54	获取价格
HY5W2A6CLF-S	HYNIX	Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54	获取价格

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