Datasheet > HMP112F7EFR8C-S5D3

HMP112F7EFR8C-S5D3

更新时间： 2024-09-14 07:04:27

品牌	Logo	应用领域
海力士 - HYNIX		光电二极管
页数	文件大小	规格书
32页	1063K
描述
Memory IC, 128MX72, CMOS, PDMA240

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

HMP112F7EFR8C-S5D3 数据手册

浏览型号HMP112F7EFR8C-S5D3的Datasheet PDF文件第2页

浏览型号HMP112F7EFR8C-S5D3的Datasheet PDF文件第3页

浏览型号HMP112F7EFR8C-S5D3的Datasheet PDF文件第4页

浏览型号HMP112F7EFR8C-S5D3的Datasheet PDF文件第5页

浏览型号HMP112F7EFR8C-S5D3的Datasheet PDF文件第6页

浏览型号HMP112F7EFR8C-S5D3的Datasheet PDF文件第7页

240pin Fully Buffered DDR2 SDRAM DIMMs based on 1Gb E-ver.

This Hynix’s Fully Buffered DIMM is a high-bandwidth & large capacity channel solution that has a narrow

host interface. Hynix’s FB-DIMM features novel architecture including the Advanced Memory Buffer that

isolates the DDR2 SDRAMs from the channel. This single component located in the front side center of

each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the

host controller and the DDR2 SDRAMs including data in and output. The AMB communicates with the host

controller and adjacent DIMMs on a system board using an industry standard Differential Point to Point

Link Interface at 1.5V power.

The AMB also allows buffering of memory traffic to support large memory capacities. All memory control

for the DDR2 SDRAM devices resides in the host, including memory request initiation, timing, refresh,

scrubbing, sparing, configuration access and power management. The AMB interface is responsible for

handling channel and memory requests to and from the local FBDIMM and for forwarding request to other

FBDIMMs on the memory channel.

FEATURES

•

240 pin Fully Buffered ECC Dual-In-Line DDR2 SDRAM Module

JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply

All inputs and outputs are compatible with SSTL_1.8 interface

Built with 1Gb DDR2 SDRAMs in 60ball FBGA

Host interface and AMB component industry standard compliant

MBIST, IBIST test functions

8 Bank architecture

OCD (Off-Chip Driver Impedance Adjustment)

ODT (On-Die Termination)

Fully differential clock operations (CK & CK)

Programmable Burst Length 4 / 8 with both sequential and interleave mode

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

Serial presence detect with EEPROM

133.35 x 30.35 mm form factor

RoHS compliant

Full DIMM Heat Spreader

This document is a general product description and is subject to change without notice. Hynix Electronics does not

assume any responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.2 / Sep. 2008

12 3 4 5 6 7...32

中文翻译

下载PDF

与HMP112F7EFR8C-S5D3相关器件

型号	品牌	获取价格	描述	数据表
HMP112F7EFR8C-S6D3	HYNIX	获取价格	240pin Fully Buffered DDR2 SDRAM DIMMs
HMP112F7EFR8C-S6D5	HYNIX	获取价格	240pin Fully Buffered DDR2 SDRAM DIMMs
HMP112F7EFR8C-Y5	HYNIX	获取价格	240pin Fully Buffered DDR2 SDRAM DIMMs
HMP112F7EFR8C-Y5D5	HYNIX	获取价格	Memory IC, 128MX72, CMOS, PDMA240
HMP112F7EFR8C-Y5N3	HYNIX	获取价格	240pin Fully Buffered DDR2 SDRAM DIMMs
HMP112P7EFR4C-S5	HYNIX	获取价格	DDR DRAM Module, 128MX8, 0.4ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240
HMP112P7EFR4C-Y5	HYNIX	获取价格	DDR DRAM Module, 128MX8, 0.4ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240
HMP112P7EFR8C-C4	HYNIX	获取价格	240pin Registered DDR2 SDRAM DIMMs
HMP112P7EFR8C-C4_1	HYNIX	获取价格	240pin Registered DDR2 SDRAM DIMMs
HMP112P7EFR8C-S5	HYNIX	获取价格	240pin Registered DDR2 SDRAM DIMMs

与HMP112F7EFR8C-S5D3相关文章

SL74HC10N：高性能三输入与非门解析
2024-09-03

78
AIC1781A 电池充电控制器深度解析
2024-09-03

69
Pickering新高压舌簧继电器亮相汽车测试博览会
2024-08-26

99
采用MCU+MPU双处理器架构实现的创新应用设计探索
2024-08-23

113

产品中心

服务支持

精选活动

关于我们

帮助中心

HMP112F7EFR8C-S5D3

HMP112F7EFR8C-S5D3 数据手册

与HMP112F7EFR8C-S5D3相关器件

与HMP112F7EFR8C-S5D3相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

HMP112F7EFR8C-S5D3

HMP112F7EFR8C-S5D3 数据手册

与HMP112F7EFR8C-S5D3相关器件

与HMP112F7EFR8C-S5D3相关文章

您还可以找

您在本页遇到什么问题？