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HMP112P7EFR4C-Y5 PDF预览

HMP112P7EFR4C-Y5

更新时间: 2024-09-15 14:51:07
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
26页 400K
描述
DDR DRAM Module, 128MX8, 0.4ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240

HMP112P7EFR4C-Y5 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM,
针数:240Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.32
风险等级:5.84Is Samacsys:N
访问模式:SINGLE BANK PAGE BURST最长访问时间:0.4 ns
其他特性:AUTO/SELF REFRESH; SEATED HGT-NOM; WD-MAXJESD-30 代码:R-PBGA-B84
长度:133.35 mm内存密度:1073741824 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:8
功能数量:1端口数量:1
端子数量:240字数:134217728 words
字数代码:128000000工作模式:SYNCHRONOUS
最高工作温度:55 °C最低工作温度:
组织:128MX8封装主体材料:UNSPECIFIED
封装代码:DIMM封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:30 mm
自我刷新:YES最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:2.7 mm
Base Number Matches:1

HMP112P7EFR4C-Y5 数据手册

 浏览型号HMP112P7EFR4C-Y5的Datasheet PDF文件第2页浏览型号HMP112P7EFR4C-Y5的Datasheet PDF文件第3页浏览型号HMP112P7EFR4C-Y5的Datasheet PDF文件第4页浏览型号HMP112P7EFR4C-Y5的Datasheet PDF文件第5页浏览型号HMP112P7EFR4C-Y5的Datasheet PDF文件第6页浏览型号HMP112P7EFR4C-Y5的Datasheet PDF文件第7页 
240pin Registered DDR2 SDRAM DIMMs based on 1Gb version E  
This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb version E DDR2  
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb  
version E based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width  
form factor of industry standard. It is suitable for easy interchange and addition.  
FEATURES  
JEDEC standard Double Data Rate2 Synchro-  
nous DRAMs (DDR2 SDRAMs) with 1.8V +/-  
0.1V Power Supply  
Fully differential clock operations (CK & CK)  
Programmable Burst Length 4 / 8 with both  
sequential and interleave mode  
All inputs and outputs are compatible with  
SSTL_1.8 interface  
Auto refresh and self refresh supported  
8192 refresh cycles / 64ms  
8 Bank architecture  
Serial presence detect with EEPROM  
DDR2 SDRAM Package: 60 ball(x4/x8)  
133.35 x 30.00 mm form factor  
Halogen free & RoHS compliant  
Posted CAS  
Programmable CAS Latency 3, 4, 5, 6  
OCD (Off-Chip Driver Impedance Adjustment)  
ODT (On-Die Termination)  
ORDERING INFORMATION  
# of  
DRAMs ranks  
# of  
Parity  
Support  
Part Name  
Density Organization  
Materials  
HMP112P7EFR8C-C4/Y5/S6/S5  
HMP125P7EFR4C-C4/Y5/S6/S5  
HMP151P7EFR4C-C4/Y5/S6/S5  
HMP31GP7EMR4C-C4/Y5  
1GB  
2GB  
4GB  
8GB  
128Mx72  
256Mx72  
512Mx72  
512Mx72  
9
1
1
2
4
Halogen Free  
Halogen Free  
Halogen Free  
Halogen Free  
O
O
O
O
18  
36  
72  
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.2 / Sep. 2008  
1

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