Datasheet > HM1-6518883

HM1-6518883

更新时间： 2024-11-15 22:33:31

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
9页	224K
描述
1024 x 1 CMOS RAM

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中文翻译

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数据手册

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HM1-6518883 数据手册

HM-6518/883

1024 x 1 CMOS RAM

March 1997

Features

Description

• This Circuit is Processed in Accordance to MIL-STD-

883 and is Fully Conformant Under the Provisions of

Paragraph 1.2.1.

The HM-6518/883 is a 1024 x 1 static CMOS RAM

fabricated using self-aligned silicon gate technology.

Synchronous circuit design techniques are employed to

achieve high performance and low power operation.

• Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max

• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max

• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max

• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min

• TTL Compatible Input/Output

On chip latches are provided for address and data outputs

allowing efﬁcient interfacing with microprocessor systems.

The data output buffers can be forced to a high impedance

state for use in expanded memory arrays.

The HM-6518/883 is a fully static RAM and may be

maintained in any state for an indeﬁnite period of time. Data

retention supply voltage and supply current are guaranteed

over temperature.

• High Output Drive - 2 TTL Loads

• High Noise Immunity

Ordering Information

• On-Chip Address Register

PART

NUMBER

• Two-Chip Selects for Easy Array Expansion

• Three-State Output

PACKAGE

TEMP. RANGE

PKG. NO.

CERDIP

-55 C to +125 C HM1-6518/883

F18.3

Pinout

HM-6518/883

(CERDIP)

TOP VIEW

18 VCC

17 S2

14 A9

13 A8

12 A7

11 A6

10 A5

GND

DESCRIPTION

Address Input

Chip Enable

Write Enable

Chip Select

Data Input

Data Output

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 2986.1

6-85

12 3 4 5 6 7...9

中文翻译

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