TM
HM-65262/883
16K x 1 Asynchronous
CMOS Static RAM
March 1997
Features
Description
• This Circuit is Processed in Accordance to MIL-STD- The HM-65262/883 is a CMOS 16384 x 1-bit Static Ran-
883 and is Fully Conformant Under the Provisions of dom Access Memory manufactured using the Intersil
Paragraph 1.2.1.
Advanced SAJI V process. The device utilizes asynchro-
nous circuit design for fast cycle times and ease of use.
The HM-65262/883 is available in both JEDEC Standard
20 pin, 0.300 inch wide CERDIP and 20 pad CLCC pack-
ages, providing high board-level packing density. Gated
inputs lower standby current, and also eliminate the need
for pull-up or pull-down resistors.
• Fast Access Time . . . . . . . . . . . . . . . . . . . 70/85nsMax
• Low Standby Current. . . . . . . . . . . . . . . . . . . . 50µA Max
• Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max
• Data Retention at 2.0V. . . . . . . . . . . . . . . . . . .20µA Max
• TTL Compatible Inputs and Outputs
• JEDEC Approved Pinout
The HM-65262/883, a full CMOS RAM, utilizes an array of
six transistor (6T) memory cells for the most stable and
lowest possible standby supply current over the full military
temperature range. In addition to this, the high stability of
the 6T RAM cell provides excellent protection against soft
errors due to noise and alpha particles. This stability also
improves the radiation tolerance of the RAM over that of
four transistor (4T) devices.
• No Clocks or Strobes Required
• Temperature Range . . . . . . . . . . . . . . . +55oC to +125oC
• Gated Inputs-No Pull-Up or Pull-Down Resistors
Required
• Equal Cycle and Access Time
• Single 5V Supply
Ordering Information
70ns/20µA
85ns/20µA
HM1-65262/883
HM4-65262/883
85ns/400µA
TEMP. RANGE
PACKAGE
CERDIP
CLCC
PKG. NO.
F20.3
o
o
-
-
-
-55 C to +125 C
o
o
HM4-65262B/883
-55 C to +125 C
J20.C
Pinouts
HM1-65262/883 (CERDIP)
TOP VIEW
HM-65262 (CLCC)
TOP VIEW
1
2
3
4
5
6
7
8
9
VCC
A13
A12
A11
20
19
18
17
A0
A1
A2
A3
A4
A5
A6
Q
2
1
20 19
A0 - A13
Address Input
A2
A3
A4
A5
A6
Q
18 A12
A11
3
4
5
6
7
8
E
Q
D
Chip Enable/Power Down
Data Out
17
16 A10
16 A10
A9
A9
A8
A7
15
14
13
Data In
15
14 A8
13 A7
VSS/GND Ground
9
10 11 12
VCC
W
Power (+5)
Write Enable
12
D
W
GND 10
11 E
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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FN3003.2
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