HM-6561/883
256 x 4 CMOS RAM
March 1997
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous
circuit design techniques are employed to achieve high per-
formance and low power operation.
• Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 200ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
On-chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays. The data inputs
and outputs are multiplexed internally for common I/O bus
compatibility.
The HM-6561/883 is a fully static RAM and may be
maintained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
• High Output Drive - 1 TTL Load
• On-Chip Address Registers
• Common Data In/Out
• Three-State Output
• Easy Microprocessor Interfacing
Ordering Information
PACKAGE TEMPERATURE RANGE
220ns
300ns
PKG. NO.
o
o
CERDIP
-55 C to +125 C
HM1-6561B/883
HM1-6561/883
F18.3
Pinout
HM-6561/883 (CERDIP)
TOP VIEW
A3
A2
1
2
3
4
5
6
7
8
9
18 VCC
17 A4
16
15 S1
A1
A0
W
A5
14 DQ3
13 DQ2
12 DQ1
11 DQ0
10 S2
A6
A7
GND
E
PIN
DESCRIPTION
A
E
Address Input
Chip Enable
Write Enable
Chip Select
Data In/Out
W
S
DQ
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2990.1
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