HM-6551/883
256 x 4 CMOS RAM
March 1997
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous cir-
cuit design techniques are employed to achieve high perfor-
mance and low power operation. On chip latches are
provided for address and data outputs allowing efficient
interfacing with microprocessor systems. The data output
buffers can be forced to a high impedance state for use in
expanded memory arrays.
• Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 220ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
The HM-6551/883 is a fully static RAM and may be main-
tained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
• High Output Drive - 1 TTL Load
• Internal Latched Chip Select
• High Noise Immunity
• On-Chip Address Register
• Latched Outputs
• Three-State Output
Ordering Information
PACKAGE
TEMPERATURE RANGE
220ns
300ns
PKG. NO.
o
o
CERDIP
-55 C to +125 C
HM-6551B/883
HM1-6551/883
F22.4
Pinout
HM-6551/883 (CERDIP)
TOP VIEW
VCC
22
A3
1
2
3
4
5
6
7
8
9
21 A4
20 W
19 S1
A2
A1
A0
A5
A6
A7
18
E
17 S2
16 Q3
15 D3
14 Q2
GND
D0
Q0 10
D1 11
13
D2
12 Q1
PIN
A
DESCRIPTION
Address Input
Chip Enable
Write Enable
Chip Select
E
W
S
D
Data Input
Q
Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2988.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19969-101