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HM1-6561/883 PDF预览

HM1-6561/883

更新时间: 2024-11-16 20:27:47
品牌 Logo 应用领域
瑞萨 - RENESAS 静态存储器内存集成电路
页数 文件大小 规格书
9页 143K
描述
256X4 STANDARD SRAM, 300ns, CDIP18, CERAMIC, DIP-18

HM1-6561/883 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:CERAMIC, DIP-18
针数:18Reach Compliance Code:not_compliant
ECCN代码:3A001.A.2.CHTS代码:8542.32.00.41
风险等级:5.88Is Samacsys:N
最长访问时间:300 nsJESD-30 代码:R-GDIP-T18
JESD-609代码:e0内存密度:1024 bit
内存集成电路类型:STANDARD SRAM内存宽度:4
功能数量:1端子数量:18
字数:256 words字数代码:256
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:256X4
输出特性:3-STATE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP18,.3
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified筛选级别:MIL-STD-883
座面最大高度:5.08 mm最大待机电流:0.00001 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.0063 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

HM1-6561/883 数据手册

 浏览型号HM1-6561/883的Datasheet PDF文件第2页浏览型号HM1-6561/883的Datasheet PDF文件第3页浏览型号HM1-6561/883的Datasheet PDF文件第4页浏览型号HM1-6561/883的Datasheet PDF文件第5页浏览型号HM1-6561/883的Datasheet PDF文件第6页浏览型号HM1-6561/883的Datasheet PDF文件第7页 
HM-6561/883  
256 x 4 CMOS RAM  
March 1997  
Features  
Description  
• This Circuit is Processed in Accordance to MIL-STD-  
883 and is Fully Conformant Under the Provisions of  
Paragraph 1.2.1.  
The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated  
using self-aligned silicon gate technology. Synchronous  
circuit design techniques are employed to achieve high per-  
formance and low power operation.  
• Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max  
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max  
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 200ns Max  
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min  
• TTL Compatible Input/Output  
On-chip latches are provided for address and data outputs  
allowing efficient interfacing with microprocessor systems.  
The data output buffers can be forced to a high impedance  
state for use in expanded memory arrays. The data inputs  
and outputs are multiplexed internally for common I/O bus  
compatibility.  
The HM-6561/883 is a fully static RAM and may be  
maintained in any state for an indefinite period of time. Data  
retention supply voltage and supply current are guaranteed  
over temperature.  
• High Output Drive - 1 TTL Load  
• On-Chip Address Registers  
• Common Data In/Out  
• Three-State Output  
• Easy Microprocessor Interfacing  
Ordering Information  
PACKAGE TEMPERATURE RANGE  
220ns  
300ns  
PKG. NO.  
o
o
CERDIP  
-55 C to +125 C  
HM1-6561B/883  
HM1-6561/883  
F18.3  
Pinout  
HM-6561/883 (CERDIP)  
TOP VIEW  
A3  
A2  
1
2
3
4
5
6
7
8
9
18 VCC  
17 A4  
16  
15 S1  
A1  
A0  
W
A5  
14 DQ3  
13 DQ2  
12 DQ1  
11 DQ0  
10 S2  
A6  
A7  
GND  
E
PIN  
DESCRIPTION  
A
E
Address Input  
Chip Enable  
Write Enable  
Chip Select  
Data In/Out  
W
S
DQ  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 2990.1  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19969-117  

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