HM-6551/883
®
Data Sheet
J uly 2003
FN2988.2
256 x 4 CMOS RAM
Features
The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous
circuit design techniques are employed to achieve high
performance and low power operation. On chip latches are
provided for address and data outputs allowing efficient
interfacing with microprocessor systems. The data output
buffers can be forced to a high impedance state for use in
expanded memory arrays.
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation. . . . . . . . . . . . . . . .20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 220ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible Input/Output
The HM-6551/883 is a fully static RAM and may be
maintained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
• High Output Drive - 1 TTL Load
• Internal Latched Chip Select
• High Noise Immunity
Ordering Information
• On-Chip Address Register
TEMP.
PKG.
• Latched Outputs
PACKAGE RANGE
220ns
300ns
DWG. #
CERDIP
-55°C to HM1-6551B/883 HM1-6551/883 F22.4
+125°C
• Three-State Output
Pinout
Pin Descriptions
HM-6551/883 (CERDIP)
PIN
DESCRIPTION
TOP VIEW
A
E
Address Input
VCC
22
21 A4
20
19 S1
18
A3
1
2
3
4
5
6
7
8
9
Chip Enable
Write Enable
Chip Select
Data Input
A2
A1
A0
A5
A6
A7
W
W
S
E
D
Q
17 S2
16 Q3
Data Output
15
14
13
D3
Q2
D2
GND
D0
Q0 10
D1 11
12 Q1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.