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HD74LS73ARPEL PDF预览

HD74LS73ARPEL

更新时间: 2024-09-16 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 93K
描述
Dual J-K Flip-Flops (with Clear)

HD74LS73ARPEL 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:3.95 X 8.65 MM, 1.27 MM PITCH, PLASTIC, SOP-14针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.17Is Samacsys:N
系列:LSJESD-30 代码:R-PDSO-G14
长度:8.65 mm逻辑集成电路类型:J-K FLIP-FLOP
最大频率@ Nom-Sup:30000000 Hz最大I(ol):0.008 A
湿度敏感等级:1位数:2
功能数量:2端子数量:14
最高工作温度:75 °C最低工作温度:-20 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):225
电源:5 V最大电源电流(ICC):6 mA
传播延迟(tpd):20 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL EXTENDED
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:3.95 mm
最小 fmax:30 MHzBase Number Matches:1

HD74LS73ARPEL 数据手册

 浏览型号HD74LS73ARPEL的Datasheet PDF文件第2页浏览型号HD74LS73ARPEL的Datasheet PDF文件第3页浏览型号HD74LS73ARPEL的Datasheet PDF文件第4页浏览型号HD74LS73ARPEL的Datasheet PDF文件第5页浏览型号HD74LS73ARPEL的Datasheet PDF文件第6页浏览型号HD74LS73ARPEL的Datasheet PDF文件第7页 
HD74LS73A  
Dual J-K Flip-Flops (with Clear)  
REJ03D0414–0300  
Rev.3.00  
Jul.22.2005  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-14 pin  
PRDP0014AB-B  
(DP-14AV)  
HD74LS73AP  
HD74LS73ARPEL  
P
PRSP0014DE-A  
(FP-14DNV)  
SOP-14 pin (JEDEC)  
RP  
EL (2,500 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Pin Arrangement  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1CK  
1CLR  
1K  
1J  
CLR  
J
Q
1Q  
1Q  
GND  
2K  
CK  
K
Q
VCC  
2CK  
2CLR  
2J  
K
Q
CK  
2Q  
2Q  
J
Q
CLR  
8
(Top view)  
Function Table  
Inputs  
Outputs  
Clear  
Clock  
J
X
L
K
X
L
Q
Q
H
L
X
L
Q0  
H
H
H
H
H
H
Q0  
L
H
L
L
H
H
X
L
H
H
X
Toggle  
H
QO  
QO  
H; high level, L; low level, X; irrelevant, ; transition from high to low level,  
Q0; level of Q before the indicated steady-state input conditions were established.  
Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established.  
Toggle; each output changes to the complement of its previous level on each active transition indicated by .  
Rev.3.00, Jul.22.2005, page 1 of 6  

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