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HD74LS75FP-EL PDF预览

HD74LS75FP-EL

更新时间: 2024-09-16 13:08:19
品牌 Logo 应用领域
瑞萨 - RENESAS 锁存器
页数 文件大小 规格书
6页 86K
描述
LS SERIES, D LATCH, PDSO16, FP-16DA

HD74LS75FP-EL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:16Reach Compliance Code:unknown
风险等级:5.68系列:LS
JESD-30 代码:R-PDSO-G16长度:10.06 mm
逻辑集成电路类型:D LATCH端子数量:16
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
认证状态:Not Qualified座面最大高度:2.2 mm
表面贴装:YES端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:5.5 mmBase Number Matches:1

HD74LS75FP-EL 数据手册

 浏览型号HD74LS75FP-EL的Datasheet PDF文件第2页浏览型号HD74LS75FP-EL的Datasheet PDF文件第3页浏览型号HD74LS75FP-EL的Datasheet PDF文件第4页浏览型号HD74LS75FP-EL的Datasheet PDF文件第5页浏览型号HD74LS75FP-EL的Datasheet PDF文件第6页 
HD74LS75  
Quadruple Bistable Latches  
REJ03D0416-0300  
Rev.3.00  
May 10, 2006  
The HD74LS75 is ideally suited for use as temporary storage for binary information between processing units and  
input / output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable  
(G) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low,  
the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the  
enable is permitted to go high. This device features complementary Q and Q outputs from a 4-bit latch.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-16 pin  
PRDP0016AE-B  
(DP-16FV)  
HD74LS75P  
HD74LS75FPEL  
P
PRSP0016DH-B  
(FP-16DAV)  
SOP-16 pin (JEITA)  
FP  
EL (2,000 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Pin Arrangement  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1Q  
1Q  
Q
D
Q
1D  
2Q  
G
G
2D  
Enable 3-4  
VCC  
2Q  
D
Q
Q
Q
Enable 1-2  
GND  
3Q  
Q
D
G
G
3D  
4D  
3Q  
D
Q
Q
4Q  
4Q  
(Top view)  
Rev.3.00, May 10, 2006, page 1 of 5  

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